System and method for reducing command scheduling constraints of memory circuits

A method, comprising:

• interfacing a first number of physical memory circuits that are associated with first command scheduling constraints, in order to simulate a different second number of virtual memory circuits that are associated with second command scheduling constraints, such that the first number of physical memory circuits appear to a system as the second number of virtual memory circuits that are associated with the second command scheduling constraints, wherein the second command scheduling constraints include fewer limitations for scheduling commands than the first command scheduling constraints,
• receiving one or more system control signals directed to at least one of the second number of virtual memory circuits;
• providing one or more physical control signals to at least one of the first number of physical memory circuits,
• wherein the first number of physical memory circuits include a first physical memory circuit, a second physical memory circuit, and a third physical memory circuit,
• wherein the interfacing further comprises electrically connecting to the first physical memory circuit, the second physical memory circuit, and the third physical memory circuit via a first data bus, a second data bus, and a third data bus, respectively,
• wherein the second number of virtual memory circuits include a first virtual memory circuit and a second virtual memory circuit,
• wherein the first virtual memory circuit is simulated using at least the first physical memory circuit, and the second virtual memory circuit is simulated using at least the second physical memory circuit and the third physical memory circuit;
• accessing data from the first physical memory circuit via the first data bus and accessing data from the second physical memory circuit via the second bus, so as to access data from the first virtual memory circuit followed by the second virtual memory circuit without an inter-device command scheduling constraint;
• and
• accessing data from the second physical memory circuit via the second data bus and accessing data from the third physical memory circuit via the third bus, so as to access data from a first row of the second virtual memory circuit followed by a second row of the second virtual memory circuit without an intra-device command scheduling constraint.

A system, comprising:

• a host system;
• a first number of physical memory circuits comprising a first physical memory circuit, a second physical memory circuit, and a third physical memory circuit;
• and
• an interface circuit electrically connected to the first physical memory circuit, the second physical memory circuit, and the third physical memory circuit via a first data bus, a second data bus, and a third data bus, respectively,
• wherein the interface circuit is configured to communicate with the first number of physical memory circuits and the host system, the interface circuit configured to interface the first number of physical memory circuits in order to simulate a different second number of virtual memory circuits that are associated with second command scheduling constraints, such that the first number of physical memory circuits appear to the host system as the second number of virtual memory circuits that are associated with the second command scheduling constraints,
• wherein the second number of virtual memory circuits include a first virtual memory circuit and a second virtual memory circuit,
• wherein the first virtual memory circuit is simulated by the interface circuit using at least the first physical memory circuit, and the second virtual memory circuit is simulated by the interface circuit using at least the second physical memory circuit and the third physical memory circuit, and
• wherein the interface circuit is configured to receive one or more system control signals directed to at least one of the second number of virtual memory circuits and to provide one or more physical control signals to at least one of the first number of physical memory circuits,
• wherein the interface circuit is configured to:
• (i) access data from the first physical memory circuit via the first data bus and access data from the second physical memory circuit via the second bus, so as to access data from the first virtual memory circuit followed by the second virtual memory circuit without an inter-device command scheduling constraint, and
• (ii) access data from the second physical memory circuit via the second data bus and access data from the third physical memory circuit via the third bus, so as to access data from a first row of the second virtual memory circuit followed by a second row of the second virtual memory circuit without an intra-device command scheduling constraint.