Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system

A method of calibrating data transfer of a memory system having a memory controller, and a memory connected to the memory controller via a connection interface, comprising:

• reading, by the memory controller, a calibration data pattern from the memory via the connection interface, according to a data transfer clock signal having a first frequency provided by a clock unit of the memory controller, wherein the calibration data pattern includes a predetermined sequence of bits;
• sampling, by an oversampling circuit of the memory controller, the calibration data pattern with a second frequency higher than the first frequency to provide an oversampled calibration data pattern;
• and
• determining, by the memory controller, a timing shift of data transfer from the memory based on the oversampled calibration data pattern.

A memory controller, comprising:

• a connection interface connected or connectable to a flash memory, the memory controller being arranged to read data from the flash memory via the connection interface;
• an instruction set storage device arranged to store an instruction set of the memory controller, the instruction set comprising one or more flexible instructions to access the flash memory,
• wherein the memory controller, in response to at least one instruction of the flexible instruction set, is configured to:
• read a calibration data pattern from the flash memory via the connection interface, according to a data transfer clock signal having a first frequency provided by a clock unit of the memory controller, wherein the calibration data pattern includes a predetermined sequence of bits;
• sampling the calibration data pattern with a second frequency higher than the first frequency to provide an oversampled calibration data pattern;
• and
• determining a timing shift of data transfer from the memory based on the oversampled calibration data pattern.