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US 9,542,343 B2Granted
Memory modules with reduced rank loading and memory systems including same
AssigneeSamsung Electronics Co., Ltd.
InventorsJeong-Kyoum Kim, In-Dal Song, Jung-Hwan Choi
Life of this patent
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Abstract
A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation.
Claims19
A memory module comprising:
- memory devices arranged on a module board in a number of ranks and a number of columns and including a first grouping of the memory devices and a second grouping of the memory devices,
- the first grouping includes memory devices arranged only in a first rank among the ranks that is nearest a memory controller that controls execution of a read operation directed to the memory devices, the second grouping includes memory devices in all ranks other than the first rank, and only the memory devices of the first rank in the first grouping are each directly connected to the memory controller,
- the memory devices in the second grouping are each indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and
- each of the memory devices in the first grouping are configured to selectively provide either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of a memory device in the second grouping during the read operation.
1 more element
A memory module comprising:
- memory devices arranged on a module board in a number of ranks and a number of columns and including a first grouping of the memory devices and a second grouping of the memory devices,
- the first grouping includes memory devices arranged in a first rank among the ranks that is nearest a memory controller that controls execution of a read operation directed to the memory devices,
- the memory devices in the first grouping are each directly connected to the memory controller,
- the memory devices in the second grouping are each indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and
- each of the memory devices in the first grouping are configured to selectively provide either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of a memory device in the second grouping during the read operation,
- wherein each of the memory devices in the first grouping comprises
- a first memory core configured to provide the self-data during the read operation;
- and
- a first path and timing adjusting circuit (PTAC) connected between the first memory core and first near data pins and first far data pins, wherein the first near data pins are configured to transmit either the self-data from the first memory core or other-data received by the first PTAC to the memory controller, and the first far data pins are configured to receive the other-data from at least one memory device in the second grouping.
6 more elements
A memory system comprising:
- a memory module comprising memory devices arranged on a module board in ranks and columns, each of the memory devices being operatively designated in one of a first grouping and a second grouping;
- and
- a memory controller configured to control execution of a read operation directed to the memory devices, wherein
- the first grouping includes only memory devices arranged in a first rank nearest the memory controller and the second grouping includes memory devices arranged in all ranks other than the first rank, and only the memory devices in the first rank of the first grouping are each directly connected to the memory controller in parallel via a corresponding data port,
- each of the memory devices in the second grouping and arranged in a same column are indirectly connected to the memory controller via a corresponding memory device in the first grouping, and
- each of the memory devices in the first grouping are configured to selectively provide either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of a memory device in the second grouping during the read operation.
3 more elements
Dependencies are inferred from the claim text.