Memory management unit TAG memory with CAM evaluate signal
AssigneeNXP USA, Inc.
InventorRavindraraj Ramaraju
Life of this patent
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Abstract
A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) having compact bitcells with embedded partial A+B=K logic to generate two speculative hit/miss signals under control of a delayed evaluate signal. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
Claims20
A method for generating a speculative miss signal from base and offset operands without requiring addition of the base and offset operands comprising:
- receiving a base operand and offset operand, wherein each operand comprises a first plurality of address bits comprising tag bits and index bits;
- pairing each address bit from the base operand with a corresponding address bit from the offset operand, thereby forming a plurality of index bit pairs and a plurality of tag bit pairs;
- applying the plurality of index bit pairs and the plurality of tag bit pairs to an indexed content-addressable memory (CAM) array to generate two speculative miss signals from two speculatively indexed rows by using a two stage dynamic comparator to generate a speculative odd miss signal and a speculative even miss signal, respectively, in response to a delayed evaluate signal that is delayed with respect to a control word line signal applied to the two speculatively indexed rows;
- and
- selecting one of the speculative odd miss signal and speculative even miss signal for output based on a sum value computed by adding at least the least significant index bit of the base operand with the least significant index bit of the offset operand.
A data processing system comprising:
- one or more processors;
- a memory array accessible by the one or more processors comprising first and second speculatively indexed content addressable memory (CAM) arrays comprising an even CAM array and an odd CAM array, each comprising a plurality of memory array entries;
- and
- selection circuitry that addresses a memory array entry from the first and second speculatively indexed CAM arrays by applying paired base and offset address bits that are not added together to the memory array using a dynamic comparator circuit to generate a speculative odd memory array entry address and a speculative even memory array entry address, respectively, in response to a delayed evaluate signal, and then selecting one of the speculative odd memory array entry address and the speculative even memory array entry address as the memory array entry for output;
- and
- an operand adder circuit placed in parallel with the selection circuit for concurrently computing an effective address by adding the base and offset address bits.
A method comprising:
- receiving a base operand and offset operand, wherein each operand comprises a first plurality of tag and index address bits;
- pairing each tag and index address bits from the base operand with a corresponding tag and index address bit from the offset operand, thereby forming a plurality of bit pairs;
- generating one or more PGZ values for each bit pair wherein a P value results from a logical XOR operation performed on each bit pair, a G value results from a logical AND operation performed on each bit pair, a Z value results from a logical AND operation performed on inverted versions of each bit pair;
- running P values, G values, and Z values generated from paired index address bits through a plurality of wordline generators to speculatively index a possible odd memory array entry address from an odd CAM array and a possible even memory array entry address from an even CAM array;
- performing fast carry generation on a second plurality of bits comprising the index address bits from the base and offset operands to generate a first carry value for the least significant tag address bits in the base and offset operands;
- generating a speculative odd miss signal and a speculative even miss signal under control of a delayed evaluate signal by applying the first carry value, along with P values and G values generated from paired tag bits, to the speculatively indexed possible odd memory array entry address from an odd CAM array and the possible even memory array entry address from an even CAM array;
- computing a sum value for the least significant index bits in the base and offset operands while generating the speculative odd miss signal and the speculative even miss signal;
- and
- selecting one of the speculative odd miss signal and speculative even miss signal based upon the sum value.
Dependencies are inferred from the claim text.