Adjustable over-restrictive cache locking limit for improved overall performance
AssigneeIntel Corporation
InventorsDaniel Greenspan, Supratik Majumder
Life of this patent
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Abstract
Disclosed is a multi-core processor that includes a processor core, a graphics core, and a cache controller. The cache controller receives a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in a cache. The cache controller sends, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device. The cache controller receives a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache. The cache controller locks the way in the second set in response to the second request.
Claims20
A multi-core processor comprising:
- a processor core;
- a graphics core;
- and
- a cache controller coupled to the processor core and the graphics core, the cache controller to:
- receive a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in a cache;
- send, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device;
- receive a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache;
- and
- lock the way in the second set in response to the second request.
A system comprising:
- main memory;
- an input-output (I/O) device;
- a cache;
- and
- a processor coupled to the cache, the I/O device, and the main memory, the processor comprising a cache controller to:
- receive a first request from the I/O device to lock a first address that corresponds to a first way in the cache;
- determine that the first way in the cache is not lockable for the I/O device;
- send, to the I/O device, a rejection of the first request;
- receive a second request from the I/O device to lock a second address that corresponds to a second way in the cache;
- and
- lock the second way in the cache in response to the second request.
A system comprising:
- main memory;
- an input-output (I/O) device;
- a cache;
- and
- a processor coupled to the cache, the I/O device, and the main memory, the processor comprising a cache controller to:
- receive a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in the cache;
- send, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device;
- receive a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache;
- and
- lock the way in the second set in response to the second request.
Dependencies are inferred from the claim text.