Address re-ordering mechanism for efficient pre-fetch training in an out-of-order processor

A computing system comprising:

• an instruction dispatch module configured to receive a program instruction;
• an address reordering module, coupled to the instruction dispatch module, configured to:
• allocate a tag in a tag module for the program instruction in a program order,
• allocate a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order,
• insert a pointer associated with the tag to link the tag to the virtual address,
• deallocate the tag from the tag module when the program instruction is repeated for prefetching, and
• collapse the tag module to maintain a relative order to the program order.

A method of operation of a computing system comprising:

• receiving a program instruction;
• filtering the program instruction when the program instruction is a hit in a cache-line in a prefetch filter;
• generating a tag for the program instruction;
• allocating the tag in a program order in a tag module;
• and
• deallocating the tag from the tag module when the program instruction is repeated for prefetching.

A method of operation of a computing system comprising:

• receiving a program instruction;
• allocating a tag in a tag module for the program instruction in a program order;
• allocating a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order;
• inserting a pointer associated with the tag to link the tag to the virtual address;
• deallocating the tag from the tag module when the program instruction is repeated for prefetching;
• and
• collapsing the tag module to maintain a relative order to the program order.