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US 9,542,305 B2Granted
Impedance matching for high speed signaling in memory system
AssigneeHarman International Industries, Incorporated
InventorThomas J. Houck
Life of this patent
Estimating the term…
Abstract
Impedance matching circuitry is positioned on a signal line intermediate the terminals of the signal line in an integrated circuit. The impedance matching circuitry can include discrete components off the integrated circuit and on a substrate, e.g., a board. The impedance matching circuitry can operate to match the impedance of a signal line in the integrated circuit, e.g., a memory device such as a DRAM or DDR DRAM.
Claims19
An electronic assembly comprising:
- a memory device including a memory cell and a first communication line in electrical communication with the memory cell, wherein the first communication line is elongated and has a first end connected to the memory cell and a second end terminating at a via;
- a substrate supporting the via and including a second communication line connected to the second end at the via and extending therefrom;
- a first impedance matching circuit including a first Thevenin network connected to the first communication line;
- and
- a second impedance matching circuit including a second Thevenin network connected to the first communication line, the second impedance matching circuit being different than the first impedance matching circuit, and the second impedance matching circuit including a plurality of different impedance paths connected at different depths to the via and selectable to tune an impedance of the second impedance matching circuit to match the second communication line.
2 more elements
A memory system comprising:
- a memory controller;
- a clock line with a first end connected to the memory controller and a second end at a via;
- a first DDR memory device connected to the second end and having a first impedance;
- a second DDR memory device connected to the second end and having a second impedance;
- a first impedance matching circuitry including a first Thevenin network connected to the second end at the via and configured to match the first impedance;
- a second impedance matching circuitry including a second Thevenin network connected to the second end at the via and configured to match the second impedance;
- wherein the via includes a plurality of connections,
- wherein the first impedance matching circuitry electrically connects at a first connection of the plurality of connections to select a first value for the first impedance;
- and
- wherein the second impedance matching circuitry electrically connects at a second connection of the plurality of connections to select a second value for the second impedance.
7 more elements
A method comprising:
- fixing a layout of a serpentine, elongate first communication line to meet electrical requirements for a high-speed system on a substrate;
- electrically connecting a memory device to a first communication line, wherein the first communication line has a first end connected to a memory cell and a second end at a via;
- electrically connecting a second communication line to the second end at a level of the via and extending therefrom;
- and
- connecting a Thevenin impedance matching circuit to the second end with the impedance matching circuit being remote from the first end and remote from a third end of the second communication line, wherein the Thevenin impedance matching circuit boosts signal integrity at the second end for both a high level and a low level, wherein the connecting at the level of the via selects an impedance matching value for the Thevenin impedance matching circuit such that the impedance can be matched free of rerouting the first communication line or the second communication by selecting the impedance matching value.
2 more elements
Dependencies are inferred from the claim text.