Dynamic data density ECC

A method of operating a memory, comprising:

• reading, in response to an address for a data set stored in a particular row of a memory array, the data set, a flag and a pointer for the data set indicating whether to use a first error correcting code (ECC) over the data set or a plurality of second ECCs for the data set, wherein each of the second ECCs is configured for use with a corresponding group of data in the data set;
• if use of the first ECC is indicated, executing ECC logic using the first ECC on the data set;
• and
• if use of the second ECCs is indicated, reading the plurality of second ECCs using the pointer, and executing the ECC logic using the second ECCs on the data set;
• wherein the first ECC is stored in the memory array, and the second ECCs are stored in memory identified by the pointer logically associated with the address for the data set indicating locations of second ECCs in the plurality of second ECCs, wherein the ECC logic applies a sequence of actions to groups of data in the data set, including applying a first action in the sequence to a group of data in the groups of data in the data set to generate a first result;
• and
• applying a subsequent second action in the sequence to generate a second result from the first result, while at a same time executing the ECC logic to apply the first action to another group of data in the groups of data in the data set.

A device, comprising:

• a memory on an integrated circuit storing a plurality of data sets, including at least one data set with a first error correcting code (ECC) over the data set, and at least one other data set with a plurality of second ECCs for the data set, each of the second ECCs in the plurality configured for use with a corresponding group of data in the one other data set, wherein data sets in the plurality of data sets have an equal size;
• and
• a controller coupled to the memory;
• wherein the first ECC is stored in the memory array, and second ECCs in the plurality of second ECCs are stored in memory identified by a pointer logically associated with an address for a corresponding data set indicating locations of second ECCs in the plurality of second ECCs, wherein the controller includes:
• logic to receive an input data set;
• and
• logic to, if use of the plurality of second ECCs is indicated, read the plurality of second ECCs and execute ECC logic using the plurality of second ECCs on the input data set;
• wherein the ECC logic applies a sequence of actions to groups of data in the data set, including applying a first action in the sequence to a group of data in the groups of data in the data set to generate a first result;
• and applying a subsequent second action in the sequence to generate a second result from the first result, while at a same time execute the ECC logic to apply the first action to another group of data in the groups of data in the data set.

A processor including:

• logic to compute and save a first error correcting code (ECC) for a data set, and to compute and save a plurality of second ECCs for the data set, each of the second ECCs configured for use with a corresponding group of data in the data set;
• logic to test the data set to determine whether to use the first ECC or the second ECCs;
• logic to execute ECC logic using the plurality of second ECCs, wherein the ECC logic applies a sequence of actions to groups of data in the data set, including applying a first action in the sequence to a group of data in the groups of data in the data set to generate a first result;
• and
• applying a subsequent second action in the sequence to generate a second result from the first result, while at a same time execute the ECC logic to apply the first action to another group of data in the groups of data in the data set,
• wherein the first ECC is stored in a memory array, and if it is determined to use the second ECCs, the second ECCs are stored in memory identified by a pointer logically associated with an address for the data set indicating locations of second ECCs in the plurality of second ECCs.