Semiconductor integrated circuit and method of processing in semiconductor integrated circuit

A method of processing in a semiconductor integrated circuit, the method comprising:

• outputting a state value depending on an input signal and outputting a parity value of the state value from a first combinational circuit in the semiconductor integrated circuit;
• storing the state value and the parity value output by the first combinational circuit in a first flip-flop circuit coupled to the first combinational circuit and outputting a first state value, a first parity value, and a first output value;
• performing a parity check based on the state value and the parity value stored in the first flip-flop circuit and outputting a first parity error when detecting an error;
• storing the state value and the parity value output by the first combinational circuit in a second flip-flop circuit coupled to the first combinational circuit in parallel with the first flip-flop circuit and outputting a second state value, a second parity value and a second output value;
• performing a parity check based on the state value and the parity value stored in the second flip-flop circuit and outputting a second parity error when detecting an error;
• allowing a selector to output the first state value to the first combinational circuit when the first parity error is not output but the second parity error is output;
• allowing the selector to output the second state value to the first combinational circuit when the first parity error is output but the second parity error is not output;
• and
• allowing the first combinational circuit to output a current state value depending on the state value output by the selector and the input signal;
• wherein
• the selector includes
• a first selector that is coupled to the first flip-flop circuit, the second flip-flop circuit, and the first parity check circuit, selects one of the first state value and the second state value based on the first parity error output from the first parity check circuit and outputs a selected state value to the first combinational circuit,
• a second selector that is coupled to the first flip-flop circuit, the second flip-flop circuit, and the first parity check circuit, selects one of the first parity value and the second parity value based on the first parity error output from the first parity check circuit and outputs a selected parity value to the first combinational circuit,
• a third selector that is coupled to the first flip-flop circuit, the second flip-flop circuit, and the first parity check circuit and selects one of the first output value and the second output value based on the first parity error output from the first parity check circuit, and
• an AND circuit that is coupled to the first parity check circuit and the second parity check circuit and outputs a result of an AND operation of the first parity error and the second parity error.