System and method for error-minimizing voltage threshold selection

A method for determining voltage thresholds in a memory device of a non-volatile memory array, the memory device comprising one or more memory cells, the method comprising:

• performing a Low-page read operation of the memory device using a Low-page voltage reference threshold to obtain a first plurality of values;
• performing a first Up-page read operation of the memory device using a first voltage threshold and a second voltage threshold to obtain a second plurality of values;
• identifying, in a first subset of bits of the second plurality of values, a first number of bit errors of a first type and a first number of bit errors of a second type, wherein the first subset of bits of the second plurality of values are identified based on corresponding bits of the first plurality of values that are set to a first state;
• identifying, in a second subset of bits of the second plurality of values, a second number of bit errors of the first type and a second number of bit errors of the second type, wherein the second subset of bits of the second plurality of values are identified based on corresponding bits of the first plurality of values that are set to a second state;
• performing a second Up-page read operation of the memory device using a third voltage threshold and a fourth voltage threshold to obtain a third plurality of values;
• identifying, in a first subset of bits of the third plurality of values, a third number of bit errors of the first type and a third number of bit errors of the second type, wherein the first subset of bits of the third plurality of values are identified based on corresponding bits of the first plurality of values that are set to the first state;
• identifying, in a second subset of bits of the third plurality of values, a fourth number of bit errors of the first type and a fourth number of bit errors of the second type, wherein the second subset of bits of the third plurality of values are identified based on corresponding bits of the first plurality of values that are set to the second state;
• performing a first linear interpolation process based on the first voltage threshold, the first number of bit errors of the first type, the first number of bit errors of the second type, the third voltage threshold, the third number of bit errors of the first type, and the third number of bit errors of the second type;
• determining a first error-minimizing voltage threshold that reduces bit errors in the first subset of bits of the second plurality of values and the first subset of bits of the third plurality of values during reads of the memory device based, at least in part, on the first linear interpolation process;
• and
• determining a second error-minimizing voltage threshold that reduces bit errors in the second subset of bits of the second plurality of values and the second subset of bits of the third plurality of values during reads of the memory device based, at least in part, on the second voltage threshold, the second number of bit errors of the first type, the second number of bit errors of the second type, the fourth voltage threshold, the fourth number of bit errors of the first type, and the fourth number of bit errors of the second type,
• wherein the method is performed under control of a controller.

A storage device comprising:

• a non-volatile memory array comprising solid state memory devices capable of being programmed with threshold values for performing read operations, each solid state memory device comprising one or more memory cells;
• and
• a controller configured to read data from the non-volatile memory array, the controller further configured to:
• perform a first read operation of a memory device from the solid state memory devices using a first voltage threshold to obtain a first plurality of values;
• identify, in the first plurality of values, a first number of bit errors of a first type and a first number of bit errors of a second type;
• perform a second read operation of the memory device using a second voltage threshold to obtain a second plurality of values, the second voltage threshold being different from the first voltage threshold;
• identify, in the second plurality of values, a second number of bit errors of the first type and a second number of bit errors of the second type;
• and
• determine an error-minimizing voltage threshold that reduces bit errors during reads of the memory device by performing a linear interpolation process, the linear interpolation process being based, at least in part, on the first voltage threshold, the first number of bit errors of the first type, the first number of bit errors of the second type, the second voltage threshold, the second number of bit errors of the first type, and the second number of bit errors of the second type.

A storage device comprising:

• a non-volatile memory array comprising solid state memory devices capable of being programmed with threshold values for performing read operations, each solid state memory device comprising one or more memory cells, the one or more memory cells comprising multi-level cells including a Low-page and an Up-page;
• and
• a controller configured to read data from the non-volatile memory array, the controller further configured to:
• perform a Low-page read operation of a memory device from the solid state memory devices using a Low-page voltage threshold to obtain a first plurality of values;
• perform a first Up-page read operation of the memory device using a first voltage threshold and a second voltage threshold to obtain a second plurality of values;
• identify, in a first subset of bits of the first plurality of values, a first number of bit errors of a first type and a first number of bit errors of a second type, wherein the first subset of bits of the second plurality of values are identified based on corresponding bits of the first plurality of values that are set to a first state;
• identify, in a second subset of bits of the second plurality of values, a second number of bit errors of the first type and a second number of bit errors of the second type, wherein the second subset of bits of the second plurality of values are identified based on corresponding bits of the first plurality of values that are set to a second state;
• perform a second Up-page read operation of the memory device using a third voltage threshold and a fourth voltage threshold to obtain a third plurality of values;
• identify, in a first subset of bits of the third plurality of values, a third number of bit errors of the first type and a third number of bit errors of the second type, wherein the first subset of bits of the third plurality of values are identified based on corresponding bits of the first plurality of values that are set to the first state;
• identify, in a second subset of bits of the third plurality of values, a fourth number of bit errors of the first type and a fourth number of bit errors of the second type, wherein the second subset of bits of the third plurality of values are identified based on corresponding bits of the first plurality of values that are set to the second state;
• perform a first linear interpolation process based on the first voltage threshold, the first number of bit errors of the first type, the first number of bit errors of the second type, the third voltage threshold, the third number of bit errors of the first type, and the third number of bit errors of the second type;
• determine a first error-minimizing voltage threshold that reduces bit errors in the first subset of bits of the second plurality of values and the first subset of bits of the third plurality of values during reads of the memory device based, at least in part, on the first linear interpolation process;
• and
• determine a second error-minimizing voltage threshold that reduces bit errors in the second subset of bits of the second plurality of values and the second subset of bits of the third plurality of values during reads of the memory device based, at least in part, on the second voltage threshold, the second number of bit errors of the first type, the second number of bit errors of the second type, the fourth voltage threshold, the fourth number of bit errors of the first type, and the fourth number of bit errors of the second type.