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US 9,542,251 B2Granted
Error detection on a low pin count bus
AssigneeOracle International Corporation
InventorScott D. Cooke
Life of this patent
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Abstract
Systems and methods that implement communication of error information on a bus, including a bus having a small number of pins are disclosed. In one embodiment, an apparatus includes an interface circuit configured to couple to a bus and one or more sideband signals. The sideband signals may be used to communicate error information such as parity information for a bus that does not otherwise have this capability. In some embodiments, parity information may be driven on the bus during a portion of a bus transaction corresponding to unused address bits.
Claims19
An apparatus, comprising:
- a communication bridge device including a bus interface circuit configured to couple to a service processor via a serial bus and first and second sideband signal lines for the serial bus, wherein the serial bus is a low pin count bus that has less than 10 signal lines, wherein the serial bus includes a set of address/data signal lines, a clock signal line, a reset signal line, and a cycle delimiter signal line, and wherein the serial bus is compatible with an Industry Standard Architecture (ISA) bus;
- wherein the bus interface circuit is further configured to use the first and second sideband signal lines to communicate error information in response to detecting an error condition on the serial bus, wherein the bus interface circuit is configured to communicate parity error information on the first and second sideband signal lines in response to detecting a parity error condition on the serial bus;
- and
- wherein the communication bridge device is configured to convey at least a portion of the parity error information during an addressing portion of a response to a bus transaction corresponding to address bits that are unused by the response to the bus transaction.
1 more element
A method, comprising:
- a service processor transmitting a read request over an ISA-compatible low pin count bus to a communication bridge device, wherein the transmitting includes the service processor transmitting information to the communication bridge device during an addressing portion of the read request, wherein the information includes an address for the read request and parity information for the read request, wherein the parity information is transmitted, via at least one of a first sideband signal line and a second sideband signal line, during a part of the addressing portion of the read request corresponding to available address bits that are unused by the address indicated by the read request;
- and
- the service processor receiving, over the low pin count bus, data from the communication bridge device that is responsive to the read request.
An apparatus, comprising:
- a service processor;
- a communication bridge device;
- a low pin count bus coupling the service processor to the communication bridge device, wherein the low pin count bus has at least 5 signal lines and no more than 10 signal lines, and wherein the low pin count bus is compatible with an Industry Standard Architecture (ISA) bus;
- and
- first and second error signal lines separate from the low pin count bus and coupling the service processor to the communication bridge device, wherein the first and second error signal lines are configured to convey information relating to errors for transactions that utilize the low pin count bus, and wherein the first and second error signal lines are sideband signal lines;
- wherein the communication bridge device is configured, in response to receiving a bus transaction from the service processor that generates an error condition, to:
- convey information via the first error signal line indicating the presence of an error for the bus transaction;
- and
- convey, via the second error signal line during a part of an addressing portion of a response to the bus transaction corresponding to available address bits that are unused by the response to the bus transaction, information indicating a type of the error.
6 more elements
Dependencies are inferred from the claim text.