System redundancy verification method and computer system
AssigneeHitachi, Ltd.
InventorsKeita Shimada, Yoshifumi Takamoto, Takashi Tameshige, Yujiro Ichikawa, Tomohito Uchida
Life of this patent
Estimating the term…
Loading patent…
AssigneeHitachi, Ltd.
InventorsKeita Shimada, Yoshifumi Takamoto, Takashi Tameshige, Yujiro Ichikawa, Tomohito Uchida
Estimating the term…
A system redundancy verification method, which is to be executed in a computer system, the computer system comprising a first computer, a second computer, a storage system, and a management computer, the system redundancy verification method including: a step of obtaining, by the management computer, first hardware information on the first computer and second hardware information on the second computer; a step of obtaining, by the management computer, first storage area information on the storage area; a step of obtaining, by the second computer the second storage area information from the storage system, and a step of comparing, by the management computer, the first hardware information and the first storage area information with the second hardware information and the second storage area information, and determining whether a failover is implementable between the first computer and the second computer.
A system redundancy verification method, which is to be executed in a computer system,
A computer system, comprising at least one first computer, at least one second computer, a storage system, and a management computer for managing the at least one first computer and the at least one second computer,
Dependencies are inferred from the claim text.