Systems and methods for direct memory access coherency among multiple processing cores
AssigneeNXP USA, Inc.
InventorsKun Xu, Tommi M. Jokinen, Zheng Xu
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AssigneeNXP USA, Inc.
InventorsKun Xu, Tommi M. Jokinen, Zheng Xu
Estimating the term…
A multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine capable of selecting, by a task scheduler of a first core, a first task for execution by the first core. In response to a semaphore lock request, the task scheduler of the first core switches the first task to an inactive state and selects a next task for execution by the first core. After the semaphore engine acquires the semaphore lock of the first semaphore, a data transfer request is provided to the DMA engine. In response to the data transfer request, the DMA engine transfers data associated with the locked first semaphore to the entry of the workspace of the first core.
In a multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine, a method comprises:
A multi-core system configured to execute a plurality of tasks, comprising:
A multi-core system configured to execute a plurality of tasks, comprising:
Dependencies are inferred from the claim text.