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US 9,542,211 B2Granted
Co-designed dynamic language accelerator for a processor
AssigneeIntel Corporation
InventorsCheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park
Life of this patent
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Abstract
In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.
Claims15
A system comprising:
- a processor to execute instructions, the processor including at least one core and a dynamic language accelerator to execute bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator, the dynamic language accelerator to receive a pathname from a virtual machine, the pathname to associate the file descriptor with the dynamic language accelerator, wherein the processor is to block execution of native code on the at least one core while the dynamic language accelerator executes is to execute the bytecode and configure, via a system call, a mapping on a native state of the processor to a virtual machine state of a virtual machine that is to trigger the dynamic language accelerator, the virtual machine a state including a bytecode state, and the processor is to associate an identifier with the virtual machine state, the processor further comprising an accelerator native interface coupled to the dynamic language accelerator, where the dynamic language accelerator is to call back to a native library via the accelerator native interface, wherein the processor is to execute a function for the virtual machine using the native library and to continue execution of the bytecode in the dynamic language accelerator after the function is executed;
- and
- system memory coupled to a processor.
A method comprising:
- configuring an accelerator mapping and a virtual machine state for a dynamic language accelerator of a processor, and associating the virtual machine state with an identifier for a virtual machine;
- executing an input/output operation to trigger execution of bytecode in the dynamic language accelerator, and blocking execution of native code on a core of the processor while the dynamic language accelerator executes the bytecode;
- calling, via an accelerator native interface of the dynamic language accelerator, a native library to handle a function for the dynamic language accelerator, wherein the processor is to execute a function for the virtual machine using the native library and to continue execution of the bytecode in the dynamic language accelerator after the function is executed;
- and
- interpreting at least one bytecode of the bytecode in the virtual machine after the dynamic language accelerator execution of at least a portion of the bytecode.
2 more elements
At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:
- configure an accelerator mapping and a virtual machine state for a dynamic language accelerator of a processor, and associate the virtual machine state with an identifier for a virtual machine;
- execute an input/output operation to trigger execution of bytecode in the dynamic language accelerator, and block execution of native code on a core of the processor while the dynamic language accelerator is to execute the bytecode;
- call, via an accelerator native interface of the dynamic language accelerator, a native library to handle a function for the dynamic language accelerator, wherein the processor is to execute a function for the virtual machine using the native library and to continue execution of the bytecode in the dynamic language accelerator after the function is executed;
- and
- interpret at least one bytecode of the bytecode in the virtual machine after the dynamic language accelerator execution of at least a portion of the bytecode.
2 more elements
Dependencies are inferred from the claim text.