Hardware profiling mechanism to enable page level automatic binary translation

A method comprising:

• identifying, by performance monitoring hardware during runtime, a code page in memory containing potentially optimizable instructions;
• requesting allocation of a new page in the memory, wherein the new page is associated with the code page, and wherein the new page contains a collection of counters and the counters correspond instructions in the code page;
• detecting a branch instruction having a branch target within the code page;
• incrementing one of the counters that has a same position in the new page as the branch target in the code page;
• repeating execution of code in the code page and incrementing the counters when branch targets fall within the code page;
• and
• providing values of the counters in the new page to a binary translator for binary translation.

A system comprising:

• memory to store a plurality of code pages;
• a processor coupled to the memory, the processor including performance monitoring hardware configured to:
• identify, during runtime, one of the code pages containing potentially optimizable instructions;
• request allocation of a new page in the memory, wherein the new page is associated with the identified code page, and wherein the new page contains a collection of counters and the counters correspond to instructions in the identified code page;
• detect a branch instruction having a branch target within the identified code page;
• increment one of the counters that has a same position in the new page as the branch target in the identified code page;
• repeat execution of code in the identified code page and incrementing the counters when branch targets fall within the identified code page;
• and
• provide values of the counters in the new page to a binary translator for binary translation.