Processor with fetch control for stoppage

A data processor comprising:

• a memory storing a program in which a plurality of instructions are written;
• an instruction cache operating only when a branch instruction included in said program is executed, data of a greater capacity, than a width of a bus of said memory being read from said memory and stored in said instruction cache in advance;
• a processing unit accessing both said memory and said instruction cache and executing, in a pipelined manner, instructions read from said memory or said instruction cache;
• and
• a fetch process control unit generating, in response to a branch instruction executed by said processing unit, a stop signal for stopping a fetch process of reading an instruction from said memory, and outputting the stop signal to said memory;
• wherein said processing unit includes:
• an instruction queue in which an instruction read from said memo is stored in advance;
• an instruction decoder successively reading instructions stored in said instruction queue and decoding the instructions;
• an instruction execution unit executing the instructions decoded by said instruction decoder;
• an instruction fetch interface unit outputting to said memory a request to read which is given from said instruction queue;
• and
• a predecoder determining whether or not an instruction to be decoded next by said instruction decoder is a branch instruction and, when said instruction is the branch instruction, said predecoder generates a stop signal the stopping said fetch process and outputs the stop signal to said instruction fetch interface unit, and
• said fetch process control unit is said predecoder;
• wherein said predecoder determines whether or not an instruction is a branch instruction by comparing an instruction to be decoded next by said instruction decoder with an instruction for which stoppage is to be effected and which is stored in advance;
• and
• wherein said predecoder adds bit information to each said instruction for which stoppage is to be effected, said bit information causing a stop signal for stopping said fetch process not to be generated even when said predecoder determines that the instruction to be decoded next is a branch instruction.