Heuristics for improving performance in a tile-based architecture
AssigneeNVIDIA Corporation
InventorsZiyad S. Hakura, Cynthia Ann Edgeworth Allison, Joseph Cavanaugh, Dale L. Kirkland, Emmett M. Kilgariff
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AssigneeNVIDIA Corporation
InventorsZiyad S. Hakura, Cynthia Ann Edgeworth Allison, Joseph Cavanaugh, Dale L. Kirkland, Emmett M. Kilgariff
Estimating the term…
One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.
A computer-implemented method for processing graphics primitives in a tile-based architecture, the method comprising:
A graphics processing pipeline, comprising:
A computing device, comprising:
Dependencies are inferred from the claim text.