Guest instruction block with near branching and far branching sequence construction to native instruction block

A processor implementing a method for translating instructions, comprising:

• a guest fetch logic component for accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, wherein the guest fetch logic component builds an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch;
• a guest fetch buffer for assembling a guest instruction block from the instruction sequence;
• a plurality of conversion tables for translating the guest instruction block to a corresponding native conversion block, wherein an at least one native far branch corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch;
• and
• wherein upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.

A microprocessor that implements a method of translating instructions, said microprocessor comprises:

• a microprocessor pipeline;
• a hardware accelerator module coupled to the microprocessor pipeline, wherein the hardware accelerator module further comprises:
• a guest fetch logic component for accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest near branch and at least one guest far branch, wherein the guest fetch logic component builds an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch;
• a guest fetch buffer for assembling a guest instruction block from the instruction sequence;
• a plurality of conversion tables for translating the guest instruction block to a corresponding native conversion block, wherein an at least one native far branch corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch;
• and
• wherein upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.

A microprocessor that implements a method of translating instructions, said microprocessor comprises:

• a microprocessor pipeline;
• a software based load store accelerator coupled to the microprocessor pipeline, wherein the load store accelerator module further comprises:
• a guest fetch logic for accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest near branch and at least one guest far branch, wherein the guest fetch logic component builds an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch;
• a guest fetch memory for assembling a guest instruction block from the instruction sequence;
• a plurality of conversion tables for translating the guest instruction block to a corresponding native conversion block, wherein an at least one native far branch corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch;
• and
• wherein upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.