Instruction set for supporting wide scalar pattern matches
AssigneeIntel Corporation
InventorsHariharan L. Thantry, Mani Azimi
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Abstract
A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit coupled to the instruction decoder to execute the instruction, the execution unit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift-left operation, to carry over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, generating a final result, and to store the final result in a storage location indicated by the first operand.
Claims18
A processor, comprising:
- an instruction decoder to decode an instruction having a first operand, a second operand, and a third operand;
- and
- an execution circuit coupled to the instruction decoder to execute the decoded instruction, the execution circuit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift operation, to carry over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, to generate a final result, and to store the final result in a storage location indicated by the first operand.
A method, comprising:
- decoding, at an instruction decoder of a processor, an instruction having a first operand, a second operand, and a third operand;
- and
- executing, by an execution unit of the processor, the decoded instruction to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift operation, carrying over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, generating a final result, and storing the final result in a storage location indicated by the first operand.
A system, comprising:
- an interconnect;
- a dynamic random access memory (DRAM) coupled to the interconnect;
- and
- a processor coupled the interconnect, including
- an instruction decoder to decode an instruction having a first operand, a second operand, and a third operand, and
- an execution circuit coupled to the instruction decoder to execute the decoded instruction, the execution circuit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage location indicated by the second operand, for each of the data elements that has an overflow in response to the shift operation, to carry over the overflow into an adjacent data element based on a first bitmask obtained from the third operand, to generate a final result, and to store the final result in a storage location indicated by the first operand.
Dependencies are inferred from the claim text.