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US 9,542,184 B2Granted
Local instruction loop buffer utilizing execution unit register file
AssigneeInternational Business Machines Corporation
InventorsAdam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
Life of this patent
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Abstract
A circuit arrangement utilizes a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to be fetched and executed directly within the execution unit, and often enabling other logic circuits utilized for other, general purpose workloads to either be powered down or freed up to handle other workloads.
Claims15
A circuit arrangement, comprising:
- a processing unit including issue logic and an execution unit, the issue logic including instruction decode logic and an instruction buffer, the issue logic configured to issue instructions from at least one instruction stream and stored in the instruction buffer to the execution unit, the execution unit including a register file within which is stored operand data, and the execution unit configured to execute the instructions issued to the execution unit by the issue logic, wherein at least a portion of the instructions executed by the execution unit manipulate the operand data stored in the register file;
- and
- control logic coupled to the execution unit and configured to utilize at least a portion of the register file as a local instruction loop buffer, wherein the control logic is configured to cause instructions stored in the register file of the execution unit to be executed by the execution unit rather than instructions stored in the instruction buffer.
An integrated circuit device, comprising:
- a processing unit including issue logic and an execution unit, the issue logic including instruction decode logic and an instruction buffer, the issue logic configured to issue instructions from at least one instruction stream and stored in the instruction buffer to the execution unit, the execution unit including a register file within which is stored operand data, and the execution unit configured to execute the instructions issued to the execution unit by the issue logic, wherein at least a portion of the instructions executed by the execution unit manipulate the operand data stored in the register file;
- and
- control logic coupled to the execution unit and configured to utilize at least a portion of the register file as a local instruction loop buffer, wherein the control logic is configured to cause instructions stored in the register file of the execution unit to be executed by the execution unit rather than instructions stored in the instruction buffer.
A program product comprising:
- a non-transitory computer readable storage medium;
- and
- logic definition program code resident on the non-transitory computer readable storage medium and defining a circuit arrangement that includes:
- a processing unit including issue logic and an execution unit, the issue logic including instruction decode logic and an instruction buffer, the issue logic configured to issue instructions from at least one instruction stream and stored in the instruction buffer to the execution unit, the execution unit including a register file within which is stored operand data, and the execution unit configured to execute the instructions issued to the execution unit by the issue logic, wherein at least a portion of the instructions executed by the execution unit manipulate the operand data stored in the register file;
- and
- control logic coupled to the execution unit and configured to utilize at least a portion of the register file as a local instruction loop buffer, wherein the control logic is configured to cause instructions stored in the register file of the execution unit to be executed by the execution unit rather than instructions stored in the instruction buffer.
3 more elements
Dependencies are inferred from the claim text.