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US 9,542,154 B2Granted
Fused multiply add operations using bit masks
AssigneeIntel Corporation
InventorsSimon Rubanovich, Thierry Pons, Amit Gradstein, Zeev Sperber
Life of this patent
Estimating the term…
Abstract
Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
Claims18
A method comprising:
- multiplying a first mantissa term of a first floating point number with a second mantissa term of a second floating point number to obtain a product;
- performing, using an adder circuit, a first logical operation on a third mantissa term of a third floating point number and a first bit mask to obtain a first bit value, wherein the adder circuit supports an argument size of less than a pre-defined value proportional to a size of one of:
- the first mantissa term, the second mantissa term, or the third mantissa term;
- performing, using a logical AND circuit, a second logical operation on the third mantissa term and an inverse of the first bit mask to produce a second bit value;
- performing, using a logical OR circuit, a third logical operation on a sum of the product with the third mantissa term and one of:
- the first bit value incremented by one or the second bit value to generate a result;
- and
- responsive to detecting an underflow, denormalizing the result using a second bit mask.
5 more elements
A system comprising:
- a set of registers to store a first floating point number, a second floating point number, and a third floating number;
- an execution unit comprising an adder circuit, the execution unit coupled to the set of registers, the execution unit to:
- multiply a first mantissa term of a first floating point number with a second mantissa term of a second floating point number to obtain a product;
- perform, using the adder circuit, a first logical operation on a third mantissa term of a third floating point number and a first bit mask to obtain a first bit value, wherein the adder circuit supports an argument size of less than a pre-defined value proportional to a size of one of:
- the first mantissa term, the second mantissa term, or the third mantissa term;
- perform, using a logical AND circuit, a second logical operation on the third mantissa term and an inverse of the first bit mask to produce a second bit value;
- perform, using a logical OR circuit, a third logical operation on a sum of the product with the third mantissa term and one of:
- the first bit value incremented by one or the second bit value to generate a result;
- and
- responsive to detecting an underflow, denormalize the result using a second bit mask.
7 more elements
A non-transitory machine-readable storage medium comprising executable instructions that, when executed by a processor, cause the processor to:
- multiply a first mantissa term of a first floating point number with a second mantissa term of a second floating point number to obtain a product;
- perform, using an adder circuit, a first logical operation on a third mantissa term of a third floating point number and a first bit mask to obtain a first bit value, wherein the adder circuit supports an argument size of less than a pre-defined value proportional to a size of one of:
- the first mantissa term, the second mantissa term, or the third mantissa term;
- perform, using a logical AND circuit, a second logical operation on the third mantissa term and an inverse of the first bit mask to produce a second bit value;
- perform, using a logical OR circuit, a third logical operation on a sum of the product with the third mantissa term and one of:
- the first bit value incremented by one or the second bit value to generate a result;
- and
- responsive to detecting an underflow, denormalize the result using a second bit mask.
5 more elements
Dependencies are inferred from the claim text.