Information processing device including host device and semiconductor memory device having a plurality of address conversion information

A memory system comprising:

• a host device having a first semiconductor memory and a first controller circuit;
• and
• a storage device being capable of communicating with the host device, the storage device having a second semiconductor memory being nonvolatile and a second controller circuit, wherein
• the first controller circuit is capable of transmitting a request for accessing to a first logical address,
• the first controller circuit is capable of transferring first information for performing the request from an area of the first semiconductor memory to the second controller circuit in response to a transfer command from the second controller circuit,
• the area has been reserved by the host device for storing data from the storage device,
• the second controller circuit is capable of receiving the request from the first controller,
• the second controller circuit is capable of determining based on second information whether the first information for performing the request is stored in the area of the first semiconductor memory, and
• the second controller circuit is capable of receiving the first information from the area of the first semiconductor memory and accessing the second semiconductor memory using the first information if the second controller circuit determines that the first information for performing the request is stored in the area of the first semiconductor memory,
• wherein the first information is address conversion information.