Controlling reduced power states using platform latency tolerance
AssigneeIntel Corporation
InventorsBarnes Cooper, Jeffrey R Wilcox, Michael N Derr, Neil W Songer, Craig S Forbell
Life of this patent
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Abstract
In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a plurality of cores;
- power management logic to:
- determine whether bus traffic is below a defined threshold level during a reduced power state in the processor;
- in response to a determination that the bus traffic is below the defined threshold level during the reduced power state in the processor, block a first plurality of break events from interrupting the reduced power state in the processor;
- in response to a first break event during the reduced power state in the processor, set an exit timer based on a platform latency tolerance and a wake time;
- and
- in response to an expiration of the exit timer, terminate the reduced power state in the processor.
A system comprising:
- a processor comprising power management logic, the power management logic to:
- determine a platform latency tolerance for a system comprising a plurality of components;
- in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance and a wake time;
- block a first plurality of break events from interrupting the reduced power state in the processor;
- in response to an expiration of the exit timer, terminate the reduced power state in the processor;
- and
- a memory coupled to the processor.
A non-transitory machine-readable medium having stored thereon data, which when used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method, comprising:
- obtaining, by power management logic of a computing system, latency tolerance information for a plurality of devices associated with the computing system;
- determining a platform latency tolerance based on the latency tolerance information;
- in response to a first break event during a reduced power state in the processor, initiating an exit timer to a time period, wherein the time period is based on the platform latency tolerance and a wake time, wherein the wake time is an amount of time to transition from the reduced power state to a normal power state;
- delaying at least one non-critical break event while the computer system is in a reduced power state;
- and
- in response to an expiration of the exit timer, terminating the reduced power state.
Dependencies are inferred from the claim text.