US 9,541,949 B2 · Synchronization of domain counters

Abstract

In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

Claims19

Dependent claims

A processor comprising:

a master counter to store a time stamp count for the processor;
a plurality of cores, each core including a core counter to store a time stamp count for the core;
and
synchronization logic to, in response to a de-synchronization event in a first core of the plurality of cores:
obtain a value of the master counter;
initiate a first core counter using the value of the master counter, wherein the first core counter is included in the first core;
compare a synchronization digit of the first core counter to a synchronization signal indicating only a value of a synchronization digit of the master counter, wherein the first core counter and the master counter each include only one synchronization digit;
and
in response to a determination that the synchronization digit of the first core counter does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal.

6 more elements

A method comprising:

in response to a de-synchronization event in a particular domain of a system, setting a domain time stamp counter equal to a value of a master time stamp counter, wherein the domain time stamp counter is to store a time stamp count for the particular domain of the system;
comparing a synchronization digit of the domain time stamp counter to a synchronization signal indicating only a value of a synchronization digit of the master time stamp counter, wherein the domain time stamp counter and the master time stamp counter each include only one synchronization digit;
and
in response to a determination that the synchronization digit of the domain counter does not match the synchronization signal, adjusting a first subset of digits of the domain counter based on a latency value of the synchronization signal.

1 more element

An apparatus comprising:

a master counter to store a first time stamp count for the apparatus;
a domain counter to store a second time stamp count for a first domain of the apparatus;
and
synchronization logic to, in response to a de-synchronization event:
obtain the first time stamp count of the master counter;
initiate the domain counter using the first time stamp count of the master counter;
compare a synchronization digit of the domain counter to a synchronization signal indicating only a value of a synchronization digit of the master counter, wherein the domain counter and the master counter each include only one synchronization digit;
and
in response to a determination that the synchronization digit of the domain counter does not match the synchronization signal, adjust a first subset of digits of the domain counter based on a latency value of the synchronization signal.

6 more elements

Dependencies are inferred from the claim text.

Synchronization of domain counters

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Synchronization of domain counters

Life of this patent

Abstract

Claims19