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US 9,538,928 B2Granted
Neural recording system
AssigneeThe Regents of the University of California
InventorsYi-Kai Lo, Wentai Liu
Life of this patent
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Abstract
A neuron recording system was provided. By using the gain-boosted topology, the amplifier input impedance can be increased while simultaneously reducing the noise. The system can be configured to record local field potentials (LFPs) and neuron spikes, respectively, with low-power consumption. With the flexible digital controller module (DCM), any subset of the recording channels can be activated for recording with independent sampling rate at each channel. A wireless interface to transmit recorded neuron data and an on-chip neuron processor to perform real-time signal processing can be incorporated in the system.
Claims15
A fully integrated neural amplifier of neural signals, comprising:
- (a) a first stage amplifier within a neural amplifier, said first stage amplifier configured for connection to a working electrode and a counter electrode, each said electrode connected to a direct current (DC) blocking capacitor (Cin) as input capacitor;
- (b) a capacitive feedback circuit within said first stage amplifier configured for setting a gain of said neural amplifier as a ratio of said input capacitor (Cin) and a feedback capacitor (Cf);
- and
- (c) a folded-cascode (FC) amplifier having an auxiliary gain stage incorporated in said first stage amplifier to increase open loop gain by using a gain booster;
- (d) wherein said gain booster comprises a first common-source (CS) amplifier, and a second common-source (CS) amplifier;
- (e) wherein said first common-source (CS) amplifier is formed by a differential pair of transistors with diode-connected load, and provides said auxiliary gain stage with additional transistors so that a first differential input is coupled to input gates of a first pair of common drain coupled transistors M1c, M1a, with a second differential input coupled to input gates of a second pair of common drain coupled transistors M1b, M1d, source connections from transistors M1c, M1d, are coupled to gates of following transistors in that same stage, while source connections from transistors M1a, M1b are output to the folded cascode stage in said second common-source (CS) amplifier in order to increase gain and reduce noise;
- (f) wherein the differential outputs of said first common-source (CS) amplifier are connected to gates of separate PMOS current source transistors M4a, M4b within said folded-cascode (FC) amplifier, which are used as the second common-source (CS) amplifier;
- (g) wherein said second common-source (CS) amplifier is embedded into a folded branch of said folded-cascode (FC) amplifier in order to minimize current consumption;
- (h) wherein said differential pair of transistors of said first common-source (CS) amplifier shares a same source with a differential pair of transistors of said auxiliary gain stage, but said auxiliary gain stage drains current with a different ratio than in said first common-source (CS) amplifier;
- and
- (i) wherein outputs from said auxiliary gain stage are coupled to said second common source amplifier at a complementary input stage providing it with increased pate-source voltage which increases transconductance.
8 more elements
A fully integrated neural amplifier for amplifying neural signals, comprising:
- (a) a first stage amplifier within a neural amplifier, said first stage amplifier configured for connection to a working electrode and a counter electrode, each said electrode connected to said first stage amplifier through a separate DC blocking capacitor (Cin), as input capacitor;
- (b) a capacitive feedback circuit within said first stage amplifier configured for setting a gain of said neural amplifier as a ratio of said input capacitor (Cin) and a feedback capacitor (Cf);
- and
- (c) a folded-cascode (FC) amplifier having an auxiliary gain stage incorporated in said first stage amplifier to increase open loop gain by using a gain booster comprising two common-source (CS) amplifiers, in which a first common-source (CS) amplifier is formed by a differential pair of transistors with diode-connected load, so that the differential outputs of said first common-source (CS) amplifier are connected to two gates of current source transistors which comprise a second common-source (CS) amplifier that is embedded into the folded branch of said folded-cascode (FC) amplifier for the purpose of minimizing current consumption;
- (d) wherein said auxiliary gain stage utilizes additional transistors so that a first differential input is coupled to input gates of a first pair of common drain coupled transistors M1c, M1a, with a second differential input coupled to input sates of a second pair of common drain coupled transistors M1b, M1d, with source connections from transistors M1c, M1d, coupled to following transistors in that same stage, while source connections from transistors M1a, M1b are output to said folded cascode amplifier in order to increase gain and reduce noise;
- (e) wherein the differential outputs of said first common-source (CS) amplifier are connected to gates of separate PMOS current source transistors M4a, M4b within said folded-cascode (FC) amplifier, which are used as the second common-source (CS) amplifier;
- (f) wherein said second common-source (CS) amplifier is embedded into a folded branch of said folded-cascode (FC) amplifier in order to minimize current consumption;
- (g) wherein said differential pair of transistors of said first common-source (CS) amplifier shares a same source with a differential pair of transistors of said auxiliary gain stage, but said auxiliary gain stage drains current with a different ratio than in said first common-source (CS) amplifier;
- (h) wherein outputs from said auxiliary gain stage are coupled to said second common source amplifier at a complementary input stage providing it with increased gate-source voltage which increases transconductance;
- and
- (i) a variable gain bandpass filter coupled to an output of said first stage amplifier, in which the variable gain bandpass filter comprises a cascade of a transconductor and a transimpedance amplifier with a load capacitor, and an RC first order high pass filter having a voltage gain determined by a product of transductance of the transconductor and the feedback resistor of the transimpedance amplifier, thus allowing variable gain to be adjusted by setting current flow in the transconductor.
8 more elements
Dependencies are inferred from the claim text.