# US 9,537,053 B2 · III nitride semiconductor device and method of manufacturing the same

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- Number: US 9,537,053 B2
- Document ID: US9537053B2
- Status: Granted
- Kind: B2
- Application number: 14/431,136
- Filed: 2012-09-28
- Published: 2015-09-17
- Granted: 2017-01-03
- Earliest claimed: 2012-09-28
- Assignees: Bbsa Limited; Dowa Electronics Materials Co., Ltd.
- Applicants: Bbsa Limited; Dowa Electronics Materials Co., Ltd.
- Inventors: Meoung Whan Cho; Seog Woo Lee; Ryuichi Toba; Yoshitaka Kadowaki
- Web page: https://patentgrep.com/patent/US9537053B2

## CPC

- H10H 20/825: containing nitrogen, e.g. GaN
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/0137: {the light-emitting regions comprising nitride materials}
- H10H 20/018: {Bonding of wafers}
- H10H 20/831: characterised by their shape
- H10H 29/14: comprising multiple light-emitting semiconductor components
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10H 20/032: {of electrodes}
- H10H 20/036: {of packages}
- H10H 20/84: Coatings, e.g. passivation layers or antireflective coatings
- H10P 14/3416: {Nitrides}
- H10P 14/61: using masks
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/10: Configurations of laterally-adjacent chips
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures.

## Claims

### Claim 1

A method of manufacturing a III nitride semiconductor device, comprising the steps of:
a step of forming a semiconductor laminate obtained by sequentially stacking a first conductivity type III nitride semiconductor layer, an active layer, and a second conductivity type III nitride semiconductor layer on a growth substrate with a lift-off layer provided therebetween;
a step of partly removing the semiconductor laminate to form a plurality of grooves in a grid pattern such that the growth substrate is partly exposed at the bottom of the grooves, thereby forming a plurality of semiconductor structures having a nearly quadrangular transverse cross-sectional shape;
a step of filling up alternate lines of the plurality of grooves in one direction with a filler;
a step of forming a support for integrally supporting the plurality of semiconductor structures by plating;
a step of forming through-holes in the support, the through-holes communicating with the filler;
a step of forming gaps by removing the filler;
a step of supplying an etchant to the gaps from the through-holes, thereby etching the lift-off layer from only one side of each of the semiconductor structures to remove the lift-off layer;
a step of forming first and second electrodes electrically connected to the first and second conductivity-type III nitride semiconductor layers, respectively; and
a singulation step for cutting the support along the plurality of grooves,
wherein in the singulation step, the support is cut along at least part of the grooves other than the grooves provided with the filler, thereby manufacturing III nitride semiconductor devices in which the cut supports support respective m rows and n columns of the semiconductor structures (where m is a natural number, and n is an even number equal to or more than 2).

### Claim 2 (depends on 1)

The method of manufacturing a III nitride semiconductor device, according to claim 1, wherein in the singulation step, the support is cut along all the grooves other than the grooves provided with the filler, thereby manufacturing a III nitride semiconductor device in which the cut supports each support two semiconductor structures.

### Claim 3 (depends on 2)

The method of manufacturing a III nitride semiconductor device, according to claim 2,
wherein at least one of the first and second electrodes also serves as the support, and
a first part of the other of the first and second electrodes that is connected to one of the semiconductor structures and a second part thereof that is connected to the other of the semiconductor structures are placed adjacent to each other.