# US 9,521,723 B2 · Integrated device comprising a matrix of OLED active pixels with improved dynamic range

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- Number: US 9,521,723 B2
- Document ID: US9521723B2
- Status: Granted
- Kind: B2
- Application number: 14/723,942
- Filed: 2015-05-28
- Published: 2015-12-17
- Granted: 2016-12-13
- Earliest claimed: 2014-06-11
- Assignees: STMicroelectronics International N.V.
- Applicants: STMicroelectronics International N.V.
- Inventors: Jerome Nebon; Christophe Forel
- Web page: https://patentgrep.com/patent/US9521723B2

## CPC

- H05B 45/60: Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An integrated device includes a semiconducting substrate having a matrix of active pixels formed therein. Each active pixel includes an OLED diode, a first nMOS transistor having its source coupled to an anode of the OLED diode, and a refresh circuit coupled to a gate of the first nMOS transistor. The first nMOS transistor has its source and its substrate coupled together. The first nMOS transistor is situated in and on a first part of the semiconductor substrate, and the refresh circuit is situated in and on a second part of the semiconductor substrate, with the first part and the second part being electrically insulated from one another.

## Claims

### Claim 1

A device, comprising:
a semiconductor substrate having first and second parts electrically insulated from one another; and
a pixel formed in the semiconductor substrate and comprising:
an OLED diode, and
a control circuit comprising:
a first transistor formed in the first part of the semiconductor substrate and having a gate, a body, and a source, the source of the first transistor being coupled to the body of the first transistor and to the OLED diode, and
a refresh circuit comprising a second transistor formed in the second part of the semiconductor substrate and being coupled to the gate of the first transistor;
wherein the first transistor is an nMOS transistor and the second transistor is an nMOS transistor.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the second transistor of the refresh circuit has a source and a drain; and wherein the refresh circuit further comprises a third transistor having a source coupled to the source of the second transistor and a drain coupled to the drain of the second transistor, wherein the third transistor is a pMOS transistor.

### Claim 3 (depends on 2)

The device according to claim 2, wherein the second and third transistors are formed in zones of the second part of the semiconductor substrate which are electrically insulated from one another.

### Claim 4 (depends on 2)

The device according to claim 2, wherein the second transistor has a body coupled to a negative potential.

### Claim 5

A device, comprising:
a semiconductor substrate having first and second parts electrically insulated from one another; and
a matrix of active pixels formed in the semiconductor substrate and comprising, for each active pixel:
an OLED diode having an anode, and
a control circuit comprising:
a first nMOS transistor having a gate, a body, and a source, the source of the first transistor being coupled to body of the first transistor and to the anode of the OLED diode, and
a refresh circuit comprising a second nMOS transistor coupled to control the gate of the first nMOS transistor;
wherein the first nMOS transistor is formed in the first part of the semiconductor substrate;
wherein the refresh circuit is formed in the second part of the semiconductor substrate.

### Claim 6 (depends on 5)

The device according to claim 5, wherein the second nMOS transistor has a source and a drain, and further comprising a pMOS transistor having a source coupled to the source of the second nMOS transistor and a drain coupled to the drain of the second nMOS transistor.

### Claim 7 (depends on 6)

The device according to claim 6, wherein the pMOS transistor and the second nMOS transistor of the refresh circuit are formed in zones of the second part of the semiconductor substrate which are electrically insulated from one another.

### Claim 8 (depends on 6)

The device according to claim 6, wherein the second nMOS transistor of the refresh circuit has a body coupled to a negative potential.

### Claim 9 (depends on 5)

The device according to claim 5, further comprising a third nMOS transistor forming a capacitor coupled between the refresh circuit and the first nMOS transistor.

### Claim 10 (depends on 9)

The device according to claim 9, wherein the third nMOS transistor is formed in a third part of the semiconductor substrate electrically insulated from the first and second parts of the semiconductor substrate.

### Claim 11 (depends on 9)

The device according to claim 9, wherein the third nMOS transistor is formed in the second part of the semiconductor substrate.

### Claim 12 (depends on 7)

The device according to claim 7, wherein the third nMOS transistor is formed in a zone of the second part of the semiconductor substrate.

### Claim 13 (depends on 12)

The device according to claim 12, wherein the first part of the semiconductor substrate is delimited by isolation trenches having an N-type doping, and wherein the pMOS transistor of the refresh circuit is formed in a deep isolation trench.

### Claim 14 (depends on 5)

The device according claim 5, wherein the first nMOS transistor is a sole transistor in the first part of the semiconductor substrate.

### Claim 15 (depends on 5)

The device according to claim 5, wherein the matrix of active pixels comprises groups of three pixels, each group of three pixels comprising a red pixel, a green pixel, and a blue pixel; and wherein the first nMOS transistors for each of the red pixel, green pixel, and blue pixel are disposed so as to form first, second, and third rectangles within the semiconductor substrate, with the first, second, and third rectangles being arranged so as to form a square.

### Claim 16

A device, comprising:
a semiconductor substrate having first and second parts electrically insulated from one another; and
a matrix of active pixels formed in the semiconductor substrate and comprising, for each active pixel:
an OLED diode having an anode, and
a control circuit comprising:
a first nMOS transistor formed in the first part of the semiconductor substrate and having a gate, a body, and a source, the source of the first nMOS transistor being coupled to body of the first nMOS transistor and to the anode of the OLED diode, and
a refresh circuit formed in the second part of the semiconductor substrate and being coupled to the gate of the first nMOS transistor, the refresh circuit comprising:
a second nMOS transistor having a gate, a body, a source, and a drain, with the gate of the second nMOS transistor being coupled to a pixel row selection line, and the body of the second nMOS transistor being coupled to a first supply voltage, and
a pMOS transistor having a gate, a body, a source, and a drain, with the gate of the pMOS transistor being coupled to a complement of the pixel row selection line, and the body of the pMOS transistor being coupled to a second supply voltage,
wherein the source and drain of the second nMOS transistor are coupled respectively to the source and drain of the pMOS transistor.

### Claim 17 (depends on 16)

The device according to claim 16, wherein the pMOS transistor and the second nMOS transistor of the refresh circuit are formed in zones of the second part of the semiconductor substrate which are electrically insulated from one another.

### Claim 18 (depends on 16)

The device according to claim 16, further comprising a third nMOS transistor forming a capacitor coupled between the refresh circuit and the first nMOS transistor.