# US 9,521,350 B2 · Solid-state imaging device and electronic apparatus

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- Number: US 9,521,350 B2
- Document ID: US9521350B2
- Status: Granted
- Kind: B2
- Application number: 14/983,111
- Filed: 2015-12-29
- Published: 2016-04-21
- Granted: 2016-12-13
- Earliest claimed: 2010-01-28
- Assignees: Sony Corporation
- Applicants: Sony Corporation
- Inventors: Hideo Kido; Atsuhiko Yamamoto; Akihiro Yamada
- Web page: https://patentgrep.com/patent/US9521350B2

## CPC

- H04N 25/767: Horizontal readout lines, multiplexers or registers
- H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N 25/7795: {Circuitry for generating timing or clock signals}
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H10F 39/15: Charge-coupled device [CCD] image sensors
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/8033: {Photosensitive area}
- H10F 39/8037: {the integrated elements comprising a transistor}
- H10F 39/80373: {characterised by the gate of the transistor}
- H10F 39/806: {Optical elements or arrangements associated with the image sensors}
- H10F 39/811: {Interconnections}
- H10F 39/813: {Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

## Claims

### Claim 1

An imaging device comprising:
a first shared pixel including:
a first plurality of photoelectric conversion portions, and
a first floating diffusion;
a second shared pixel disposed adjacent to the first shared pixel and including:
a second plurality of photoelectric conversion portions, and
a second floating diffusion; and
a transistor portion, the transistor portion including a first reset transistor, a second reset transistor, and an amplification transistor,
wherein a gate terminal of the amplification transistor is disposed in a first row located between the first shared pixel and the second shared pixel, and
wherein a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed separated from one another in a second row.

### Claim 2 (depends on 1)

The imaging device according to claim 1, wherein the first shared pixel or the second shared pixel is disposed between the first row and the second row.

### Claim 3 (depends on 1)

The imaging device according to claim 1, wherein the transistor portion further includes a selection transistor, wherein a gate terminal of the selection transistor is disposed in the first row.

### Claim 4 (depends on 1)

The imaging device according to claim 1, wherein the first shared pixel further includes a first transfer transistor disposed between the first plurality of photoelectric conversion portions and the first floating diffusion, and the second shared pixel further includes a second transfer transistor disposed between the second plurality of photoelectric conversion portions and the second floating diffusion.

### Claim 5 (depends on 1)

The imaging device according to claim 1, wherein the first plurality of photoelectric conversion portions includes four photoelectric conversion portions, and the second plurality of photoelectric conversion portions includes four photoelectric conversion portions.

### Claim 6 (depends on 1)

The imaging device according to claim 1, wherein the first reset transistor and the second reset transistor are connected to a power source line at a connection point located between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

### Claim 7 (depends on 6)

The imaging device according to claim 6, wherein the first reset transistor and the second reset transistor share a common drain terminal, and the common drain terminal is disposed between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

### Claim 8 (depends on 6)

The imaging device according to claim 6, wherein the connection point is located at the common drain terminal.

### Claim 9 (depends on 1)

The imaging device according to claim 1, further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the first side of the semiconductor substrate.

### Claim 10 (depends on 1)

The imaging device according to claim 1, further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the second side of the semiconductor substrate.

### Claim 11

An electronic apparatus comprising:
an imaging device;
an optical system configured to guide incident light to the imaging device; and
a signal processing circuit configured to process an output signal of the imaging device,
wherein the imaging device includes:
a first shared pixel including:
a first plurality of photoelectric conversion portions, and
a first floating diffusion;
a second shared pixel disposed adjacent to the first shared pixel and including:
a second plurality of photoelectric conversion portions, and
a second floating diffusion; and
a transistor portion, the transistor portion including a first reset transistor, a second reset transistor, and an amplification transistor,
wherein a gate terminal of the amplification transistor is disposed in a first row located between the first shared pixel and the second shared pixel, and
wherein a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed separated from one another in a second row.

### Claim 12 (depends on 11)

The electronic apparatus according to claim 11, wherein the first shared pixel or the second shared pixel is disposed between the first row and the second row.

### Claim 13 (depends on 11)

The electronic apparatus according to claim 11, wherein the transistor portion further includes a selection transistor, wherein a gate terminal of the selection transistor is disposed in the first row.

### Claim 14 (depends on 11)

The electronic apparatus according to claim 11, wherein the first shared pixel further includes a first transfer transistor disposed between the first plurality of photoelectric conversion portions and the first floating diffusion, and the second shared pixel further includes a second transfer transistor disposed between the second plurality of photoelectric conversion portions and the second floating diffusion.

### Claim 15 (depends on 11)

The electronic apparatus according to claim 11, wherein the first plurality of photoelectric conversion portions includes four photoelectric conversion portions, and the second plurality of photoelectric conversion portions includes four photoelectric conversion portions.

### Claim 16 (depends on 11)

The electronic apparatus according to claim 11, wherein the first reset transistor and the second reset transistor are connected to a power source line at a connection point located between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

### Claim 17 (depends on 16)

The electronic apparatus according to claim 16, wherein the first reset transistor and the second reset transistor share a common drain terminal, and the common drain terminal is disposed between the gate terminal of the first reset transistor and the gate terminal of the second reset transistor.

### Claim 18 (depends on 16)

The electronic apparatus according to claim 16, wherein the connection point is located at the common drain terminal.

### Claim 19 (depends on 11)

The electronic apparatus according to claim 11, further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the first side of the semiconductor substrate.

### Claim 20 (depends on 11)

The electronic apparatus according to claim 11, further comprising:
a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and
a wiring layer disposed adjacent to the second side of the semiconductor substrate.