# US 9,521,058 B2 · Multi-wire signaling with matched propagation delay among wire pairs > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,521,058 B2 - Document ID: US9521058B2 - Status: Granted - Kind: B2 - Application number: 15/097,027 - Filed: 2016-04-12 - Published: 2016-08-04 - Granted: 2016-12-13 - Earliest claimed: 2014-06-25 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Shree Krishna Pandey; Arun Chandra Kundu; George Alan Wiley; Chulkyu Lee - Web page: https://patentgrep.com/patent/US9521058B2 ## CPC - H04L 43/087: Jitter - G06F 13/40: Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} - H04B 3/00: Line transmission systems (combined with near-field transmission systems H04B5/00) - H04B 3/462: Testing group delay or phase shift, e.g. timing jitter - H04B 3/542: {the information being in digital form} - H04L 25/0264: {Arrangements for coupling to transmission lines (duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878)} - H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} - H04L 7/0041: {Delay of data signal} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04B: TRANSMISSION ## Abstract In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques. ## Claims ### Claim 1 An apparatus for multi-wire signaling, comprising: a plurality of wires comprising at least one middle wire, a first outer wire located adjacent to one side of the at least one middle wire, and a second outer wire located adjacent to another side of the at least one middle wire; and at least one delay element coupled to at least one of the plurality of wires, wherein the at least one delay element provides an amount of signal delay such that a signal propagation time associated with the at least one middle wire is less than a signal propagation time associated with at least one of the first outer wire or the second outer wire and signal propagation times associated with wire pairs of the plurality of wires are equal to one another within a margin of error. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the at least one delay element comprises a passive delay structure. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the at least one delay element comprises a wire of a defined length such that an overall length of the at least one middle wire is shorter than a length of the first outer wire and the second outer wire. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the at least one delay element comprises an active delay device. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the at least one delay element comprises a programmable delay device; and the apparatus further comprises a delay controller to generate at least one control signal to control a delay of the at least one delay element. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising a driver circuit coupled to the plurality of wires and configured to, for a particular data transfer, drive a particular one of the wire pairs of the plurality of wires, whereby every other wire of the plurality of wires is in a high impedance state, wherein the driver circuit embodies the at least one delay element. ### Claim 7 (depends on 1) The apparatus of claim 1, further comprising a receiver circuit coupled to the plurality of wires and configured to decode information for a particular data transfer based on a particular one of the wire pairs of the plurality of wires being driven, and every other wire of the plurality of wires being in a high impedance state. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the receiver circuit comprises at least one differential receiver and the at least one delay element is coupled to an output of the at least one differential receiver. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the at least one delay element comprises a delay element coupled to at least one of the first outer wire or the second outer wire. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the at least one middle wire comprises at least two middle wires. ### Claim 11 A method for multi-wire signaling, comprising: determining signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least one middle wire, a first outer wire located adjacent to one side of the at least one middle wire, and a second outer wire located adjacent to another side of the at least one middle wire; and specifying a delay for at least one delay element coupled to at least one of the plurality of wires, wherein the at least one delay element provides an amount of signal delay such that a signal propagation time associated with the at least one middle wire is less than a signal propagation time associated with at least one of the first outer wire or the second outer wire and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error. ### Claim 12 (depends on 11) The method of claim 11, wherein the at least one delay element comprises a wire of a defined length such that an overall length of the at least one middle wire is shorter than a length of the first outer wire and the second outer wire. ### Claim 13 (depends on 11) The method of claim 11, wherein: the at least one delay element has a programmable delay; and the specification of the delay comprises controlling the programmable delay of the at least one delay element. ### Claim 14 (depends on 11) The method of claim 11, further comprising driving a particular one of the wire pairs of the plurality of wires for a particular data transfer, whereby every other wire of the plurality of wires is in a high impedance state. ### Claim 15 (depends on 11) The method of claim 11, further comprising decoding information for a particular data transfer based on a particular one of the wire pairs of the plurality of wires being driven, and every other wire of the plurality of wires being in a high impedance state. ### Claim 16 (depends on 15) The method of claim 15, wherein the information is decoded via a receiver circuit coupled to the plurality of wires, wherein the receiver circuit comprises at least one differential receiver and the at least one delay element is coupled to an output of the at least one differential receiver. ### Claim 17 (depends on 11) The method of claim 11, wherein the at least one delay element comprises a delay element coupled to at least one of the first outer wire or the second outer wire. ### Claim 18 (depends on 11) The method of claim 11, wherein the at least one middle wire comprises at least two middle wires. ### Claim 19 An apparatus for multi-wire signaling, comprising: a communication interface circuit; and a processing circuit configured to via the communication interface circuit: determine signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least one middle wire, a first outer wire located adjacent to one side of the at least one middle wire, and a second outer wire located adjacent to another side of the at least one middle wire, and specify a delay for at least one delay element coupled to at least one of the plurality of wires, wherein the at least one delay element provides an amount of signal delay such that a signal propagation time associated with the at least one middle wire is less than a signal propagation time associated with at least one of the first outer wire or the second outer wire and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the at least one delay element comprises a wire of a defined length such that an overall length of the at least one middle wire is shorter than a length of the first outer wire and the second outer wire. ### Claim 21 (depends on 19) The apparatus of claim 19, wherein: the at least one delay element has a programmable delay; and the specification of the delay comprises controlling the programmable delay of the at least one delay element. ### Claim 22 (depends on 19) The apparatus of claim 19, the processing circuit further configured to drive a particular one of the wire pairs of the plurality of wires for a particular data transfer, whereby every other wire of the plurality of wires is in a high impedance state. ### Claim 23 (depends on 19) The apparatus of claim 19, the processing circuit further configured to decode information for a particular data transfer based on a particular one of the wire pairs of the plurality of wires being driven, and every other wire of the plurality of wires being in a high impedance state. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the information is decoded via a receiver circuit coupled to the plurality of wires, wherein the receiver circuit comprises at least one differential receiver and the at least one delay element is coupled to an output of the at least one differential receiver. ### Claim 25 (depends on 23) The apparatus of claim 23, wherein the at least one delay element comprises a delay element coupled to at least one of the first outer wire or the second outer wire. ### Claim 26 (depends on 23) The apparatus of claim 23, wherein the at least one middle wire comprises at least two middle wires. ### Claim 27 An apparatus for multi-wire signaling, comprising: means for determining signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least one middle wire, a first outer wire located adjacent to one side of the at least one middle wire, and a second outer wire located adjacent to another side of the at least one middle wire; and means for specifying a delay for at least one delay element coupled to at least one of the plurality of wires, wherein the at least one delay element provides an amount of signal delay such that a signal propagation time associated with the at least one middle wire is less than a signal propagation time associated with at least one of the first outer wire or the second outer wire and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error. ### Claim 28 (depends on 27) The apparatus of claim 27, wherein the at least one delay element comprises a wire of a defined length such that an overall length of the at least one middle wire is shorter than a length of the first outer wire and the second outer wire. ### Claim 29 (depends on 27) The apparatus of claim 27, further comprising means for driving a particular one of the wire pairs of the plurality of wires for a particular data transfer, whereby every other wire of the plurality of wires is in a high impedance state. ### Claim 30 (depends on 27) The apparatus of claim 27, further comprising means for decoding information for a particular data transfer based on a particular one of the wire pairs of the plurality of wires being driven, and every other wire of the plurality of wires being in a high impedance state, wherein the information is decoded via a receiver circuit coupled to the plurality of wires, wherein the receiver circuit comprises at least one differential receiver and the at least one delay element is coupled to an output of the at least one differential receiver.