# US 9,521,021 B2 · Adaptive backchannel equalization

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- Number: US 9,521,021 B2
- Document ID: US9521021B2
- Status: Granted
- Kind: B2
- Application number: 14/859,339
- Filed: 2015-09-20
- Published: 2016-03-17
- Granted: 2016-12-13
- Earliest claimed: 2013-03-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Yun He; Sanjib Sarkar
- Web page: https://patentgrep.com/patent/US9521021B2

## CPC

- H04L 25/03878: {Line equalisers; line build-out devices}
- H04L 25/03343: {Arrangements at the transmitter end}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.

## Claims

### Claim 1

At least one non-transitory machine accessible storage medium having code stored thereon, the code when executed on a machine, causes the machine to:
determine a continuous time linear equalizer (CTLE) peak setting of a receiver, wherein the receiver is coupled to a transmitter by a serial link; and
transmit data over the serial link based on the transmitter equalization coefficient and the CTLE peak setting,
wherein determining the continuous time linear equalizer (CTLE) peak setting comprises determining a continuous time linear equalizer (CTLE) peak value change by:
increasing the CTLE peak value if a first decision feedback equalizer (DFE) tap exceeds a first preselected percentage of maximum capacity; and
decreasing the CTLE peak value if a second DFE tap has an opposite magnitude as the first DFE tap and exceeds a second preselected percentage of the first DFE first tap magnitude.

### Claim 2 (depends on 1)

The storage medium of claim 1, wherein the code, when executed, further causes the machine to determine a total equalization value over a training period.

### Claim 3 (depends on 2)

The storage medium of claim 2, wherein the code, when executed, further causes the machine to determine a total balance equalization value over the preselected training period.

### Claim 4 (depends on 3)

The storage medium of claim 3, wherein the code, when executed, further causes the machine to determine a transmitter equalization coefficient of a transmitter based on the total equalization value and the total balance equalization value.

### Claim 5 (depends on 3)

The storage medium of claim 3, wherein determining a balance equalization value over a preselected training period comprises:
for each interval within the preselected training period determining a balance equalization detection value for the interval; and
summing the balance equalization value for multiple intervals to determine the balance equalization value over the preselected training period.

### Claim 6 (depends on 5)

The storage medium of claim 5, wherein the balance equalization detection value for the interval is a positive value if a first center bit of two center bits in a multi-bit pattern exceeds a reference voltage value and a second center bit of the two center bits is less than the reference voltage.

### Claim 7 (depends on 5)

The storage medium of claim 5, wherein the balance equalization detection value for the interval is a negative value if a first center bit of two center bits in a multi-bit pattern is less than a reference voltage value and a second center bit of the two center bits exceeds the reference voltage.

### Claim 8 (depends on 1)

The storage medium of claim 1, wherein the first preselected percentage and the second preselected percentage are programmable.

### Claim 9 (depends on 1)

The storage medium of claim 1, wherein the serial link comprises a Peripheral Component Interconnect (PCI) compliant link.

### Claim 10 (depends on 9)

The storage medium of claim 9, wherein the PCI compliant link comprises a PCI express (PCIe), third generation or greater compliant link.

### Claim 11

A method comprising:
determining a continuous time linear equalizer (CTLE) peak setting of a receiver, wherein the receiver is coupled to a transmitter by a serial link; and
transmitting data over the serial link based on the transmitter equalization coefficient and the CTLE peak setting,
wherein determining the continuous time linear equalizer (CTLE) peak setting comprises determining a continuous time linear equalizer (CTLE) peak value change by:
increasing the CTLE peak value if a first decision feedback equalizer (DFE) tap exceeds a first preselected percentage of maximum capacity; and
decreasing the CTLE peak value if a second DFE tap has an opposite magnitude as the first DFE tap and exceeds a second preselected percentage of the first DFE first tap magnitude.

### Claim 12 (depends on 11)

The method of claim 11, further comprising determining a total equalization value over a training period.

### Claim 13 (depends on 12)

The method of claim 12, further comprising determining a total balance equalization value over the preselected training period.

### Claim 14 (depends on 13)

The method of claim 13, further comprising determining a transmitter equalization coefficient of a transmitter based on the total equalization value and the total balance equalization value.

### Claim 15 (depends on 14)

The method of claim 14, wherein the transmitter equalization coefficient is determined by detecting total equalization and balance equalization and further determining a transmitter equalization coefficient de-emphasis coefficient change (Δcp1), a transmitter equalization coefficient pre-shoot coefficient change (Δcm1), and a main tap change value (Δc0) using equations:
{
Δ
⁢
⁢
1
=
sign
⁡
(
teq_total
)
Δ
⁢
⁢
2
=
sign
⁡
(
beq_total
)
Δ
⁢
⁢
cp
⁢
⁢
1
+
Δ
⁢
⁢
cm
⁢
⁢
1
=
Δ
⁢
⁢
1
Δ
⁢
⁢
cp
⁢
⁢
1
-
Δ
⁢
⁢
cm
⁢
⁢
1
=
Δ
⁢
⁢
2
→
{
Δ
⁢
⁢
cp
⁢
⁢
1
=
sign
⁡
(
Δ
⁢
⁢
1
+
Δ
⁢
⁢
2
)
Δ
⁢
⁢
cm
⁢
⁢
1
=
sign
⁡
(
Δ
⁢
⁢
1
-
Δ
⁢
⁢
2
)
Δ
⁢
⁢
c
⁢
⁢
0
=
-
(
Δ
⁢
⁢
cp
⁢
⁢
1
+
Δ
⁢
⁢
cm
⁢
⁢
1
)
wherein teq_total comprises a total equalization value and beq_total comprises a balance equalization value.

### Claim 16 (depends on 13)

The method of claim 13, wherein determining a balance equalization value over a preselected training period comprises:
for each interval within the preselected training period determining a balance equalization detection value for the interval; and
summing the balance equalization value for multiple intervals to determine the balance equalization value over the preselected training period.

### Claim 17 (depends on 11)

The method of claim 11, wherein the first preselected percentage and the second preselected percentage are programmable.

### Claim 18

An apparatus comprising:
a feed forward equalizer module to:
determine a continuous time linear equalizer (CTLE) peak setting of a receiver, by determining a continuous time linear equalizer (CTLE) peak value change, wherein determining the CTLE peak value change comprises:
increasing the CTLE peak value if a first decision feedback equalizer (DFE) tap exceeds a first preselected percentage of maximum capacity; and
decreasing the CTLE peak value if a second DFE tap has an opposite magnitude as the first DFE tap and exceeds a second preselected percentage of the first DFE first tap magnitude; and
a link controller to cause data to be transmitted over a serial link based at least in part on the CTLE peak setting.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the feed forward equalizer module is further to:
determine a total equalization value over a training period,
determine a total balance equalization value over the preselected training period, and
determine a transmitter equalization coefficient of a transmitter based on the total equalization value and the total balance equalization value.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the link controller causes data to be transmitted over the serial link further based on the total balance equalization value.