# US 9,520,971 B2 · Data transmission method and device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,971 B2 - Document ID: US9520971B2 - Status: Granted - Kind: B2 - Application number: 14/415,619 - Filed: 2012-07-17 - Published: 2015-06-25 - Granted: 2016-12-13 - Earliest claimed: 2012-07-17 - Assignees: Zte Corporation - Applicants: Peng Hao; Lining Yang; Can Huang; Zhen Gao - Inventors: Peng Hao; Lining Yang; Can Huang; Zhen Gao - Web page: https://patentgrep.com/patent/US9520971B2 ## CPC - H04L 5/0044: {Allocation of payload; Allocation of data channels, e.g. PDSCH or PUSCH} - H04J 3/047: {Distributors with transistors or integrated circuits} - H04J 3/1605: {Fixed allocated frame structures} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract Provided is a data transmission method and device. The method includes: receiving IQ data from an uplink; according to the mapping of the IQ data in a Common Public Radio Interface (CPRI) basic frame, utilizing at least one storage unit to sequence the IQ data; combining a control word with the sequenced IQ data to form CPRI data, and transmitting the CPRI data. The solution utilizes at least one storage unit to sequence the IQ data, and extracts the sequenced data for a CPRI framing operation. This solution is simple in hardware processing and low in realization complexity. The change and upgrade of the transmission bandwidth of multiple modes (single mode or mixed mode) during system upgrade only occur on software layer without affecting the realization of hardware, thus having good flexibility. ## Claims ### Claim 1 A data transmission method, comprising: receiving orthogonal in-phase and quadrature (IQ) data from an uplink; according to mapping of the IQ data in a Common Public Radio Interface (CPRI) basic frame, utilizing at least one storage unit to sequence the IQ data; combining a control word with the sequenced IQ data to form CPRI data, and transmitting the CPRI data; wherein according to the mapping of the IQ data in the CPRI basic frame, utilizing the at least one storage unit to sequence the IQ data comprises: sampling the IQ data; according to the mapping of the IQ data in the CPRI basic frame, respectively extracting each bit in the sampled IQ data of one clock cycle; respectively storing the each bit in different storage units; and instructing hardware to read in one clock cycle all bits of a same carrier from the different storage units to form carrier data. ### Claim 2 (depends on 1) The method according to claim 1, wherein instructing the hardware to read in one clock cycle all the bits of the same carrier from the different storage units to form the carrier data comprises: instructing, through a register, the hardware to read in one clock cycle all the bits of the same carrier from the different storage units to form the carrier data. ### Claim 3 (depends on 2) The method according to claim 2, wherein the at least one storage unit is Radom Access Memory (RAM). ### Claim 4 (depends on 1) The method according to claim 1, wherein the at least one storage unit is Radom Access Memory (RAM). ### Claim 5 (depends on 1) The method according to claim 1, wherein the at least one storage unit is Radom Access Memory (RAM). ### Claim 6 A base station, comprising a processor configured to execute program modules stored on a memory, the program modules comprising: a receiving module, which is configured to receive orthogonal in-phase and quadrature (IQ) data from an uplink; a sequencing module, which is configured to, according to mapping of the IQ data in a Common Public Radio Interface (CPRI) basic frame, utilize at least one storage unit to sequence the IQ data; a combining module, which is configured to combine a control word with the sequenced IQ data to form CPRI data; and a transmitting module, which is configured to transmit the CPRI data; wherein the sequencing module includes: a sampling unit, which is configured to sample the IQ data; an extracting unit, which is coupled with the sampling unit and configured to, according to the mapping of the IQ data in the CPRI basic frame, respectively extract each bit in the sampled IQ data of one clock cycle; a storage unit, which is coupled with the extracting unit and configured to respectively store the each bit in different storage units; and an instructing unit, which is coupled with the at least one storage unit and configured to instruct the hardware to read in one clock cycle all bits of the same carrier from the different storage units to form carrier data. ### Claim 7 A data transmission method, comprising: receiving Common Public Radio Interface (CPRI) data, and separating a control word in the CPRI data from orthogonal in-phase and quadrature (IQ) data; constructing information which is the same as mapping of the IQ data in a CPRI basic frame, and utilizing at least one storage unit to sequence the IQ data; and transmitting the sequenced IQ data; wherein utilizing the at least one storage unit to sequence the IQ data comprises: sampling the IQ data instructing hardware to respectively extract each bit in the sampled IQ data of one clock cycle; respectively writing each bit in different storage units; and reading in one clock cycle all bits of a same carrier from the different storage units, and combining all the bits to form carrier data. ### Claim 8 (depends on 7) The method according to claim 7, wherein constructing the information which is the same as the mapping of the IQ data in the CPRI basic frame comprises: constructing, according to a current mode and bit width, the information which is the same as the mapping of the IQ data in the CPRI basic frame. ### Claim 9 (depends on 8) The method according to claim 8, wherein the at least one storage unit is Radom Access Memory (RAM). ### Claim 10 (depends on 7) The method according to claim 7, wherein reading all the bits of the same carrier from the different storage units comprises: instructing, through a register, the hardware to read in one clock cycle all the bits of the same carrier from the different storage units. ### Claim 11 (depends on 10) The method according to claim 10, wherein the at least one storage unit is Radom Access Memory (RAM). ### Claim 12 (depends on 7) The method according to claim 7, wherein the at least one storage unit is Radom Access Memory (RAM). ### Claim 13 (depends on 5) The method according to claim 5, wherein the at least one storage unit is Radom Access Memory (RAM). ### Claim 14 A base station, comprising a processor configured to execute program modules stored on a memory, the program modules comprising: a receiving module, which is configured to receive Common Public Radio Interface (CPRI) data; a separating module, which is configured to separate a control word in the CPRI data from orthogonal in-phase and quadrature (IQ) data; a constructing module, which is configured to construct information which is the same as mapping of the IQ data in a CPRI basic frame; a sequencing module, which is configured to utilize at least one storage unit to sequence the IQ data; and a transmitting module, which is configured to transmit the sequenced IQ data; wherein the sequencing module includes: a sampling unit, which is configured to sample the IQ data; an extracting unit, which is coupled with the sampling unit and configured to, according to the mapping of the IQ data in the CPRI basic frame, respectively extract each bit in the sampled IQ data of one clock cycle; a storage unit, which is coupled with the extracting unit and configured to respectively store the each bit in different storage units; and an instructing unit, which is coupled with the at least one storage unit and configured to instruct the hardware to read in one clock cycle all bits of the same carrier from the different storage units to form carrier data.