# US 9,520,965 B2 · Monitoring and control of reference clocks to reduce bit error ratio

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- Number: US 9,520,965 B2
- Document ID: US9520965B2
- Status: Granted
- Kind: B2
- Application number: 14/587,477
- Filed: 2014-12-31
- Published: 2016-06-30
- Granted: 2016-12-13
- Earliest claimed: 2014-12-31
- Assignees: Ciena Corporation
- Applicants: Shawn Barrow
- Inventors: Shawn Barrow
- Web page: https://patentgrep.com/patent/US9520965B2

## CPC

- H04L 1/0036: {arrangements specific to the receiver}
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03M 1/0639: {using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M1/201)}
- H04L 1/00: Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)}
- H04L 1/0046: {Code rate detection or code type detection (H04L1/0038 takes precedence; detection of the data rate H04L25/0262; for packet format H04L1/0091)}
- H04L 1/20: using signal quality detector
- H04L 7/0054: {Detection of the synchronisation error by features other than the received signal transition (by means of signal transition H04L7/033)}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation}
- H04L 7/048: {using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)

## Abstract

A method for reducing a frequency error, including: applying a plurality of dither values to a local reference clock over a first time interval; sampling, during the first time interval and using the local reference clock, a first plurality of data values received over an asynchronous link, where the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; tracking a plurality of errors from sampling the first plurality of data values; and adjusting, based on the plurality of errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

## Claims

### Claim 1

A method for reducing a frequency error, comprising:
applying a plurality of dither values to a local reference clock over a first time interval by:
applying, by modifying a divider, a first set of positive dither values during a first half of the first time interval, and
applying, by modifying the divider, a second set of negative dither values during a second half of the first time interval;
sampling, during the first time interval and using the local reference clock, a first plurality of data values received over an asynchronous link, wherein the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock;
tracking a plurality of bit errors from the sampling of the first plurality of data values; and
adjusting, based on the plurality of bit errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first set of positive dither values has a maximum dither value of 1.0 parts per million (PPM), wherein two consecutive positive dither values have a step size of 100 parts per billion (PPB), and wherein the plurality of dither values form a triangular wave.

### Claim 3 (depends on 1)

The method of claim 1, wherein applying the first set of positive dither values comprises:
modifying a numerator of the divider in a clock synthesizer integrated circuit of the local reference clock.

### Claim 4 (depends on 1)

The method of claim 1, wherein tracking the plurality of bit errors comprises:
counting a first number of bit errors during the first half of the first time interval;
counting a second number of bit errors during the second half of the first time interval; and
generating a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the adjusting of the frequency of the local reference clock is based on the comparison.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
applying, after adjusting the frequency of the local reference clock, the first set of positive dither values to the local reference clock during a first half of a second time interval;
applying, after adjusting the frequency of the local reference clock, the second set of negative dither values to the local reference clock during a second half of the second time interval;
sampling, during the second time interval and using the local reference clock, a second plurality of data values received over the asynchronous link, wherein the second plurality of data values are transmitted over the asynchronous link based on the remote reference clock;
counting a first number of bit errors from the sampling of the second plurality of data values during the first half of the second time interval;
counting a second number of bit errors from the sampling of the second plurality of data values during the second half; and
generating a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the comparison indicates that the first number of bit errors and the second number of bit errors are balanced.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
issuing, by a first line module comprising the local reference clock, an alert based on repeated adjustments to the local reference clock, wherein the remote reference clock is located in a switch module connected to the first line module and a second line module, and
wherein failure of a crystal in the local reference clock is detected based on the alert from the first line module and no alert from the second line module.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
issuing, by a first line module comprising the local reference clock, a first alert based on repeated adjustments to the local reference clock, wherein the remote reference clock is located in a switch module connected to the first line module and a second line module, wherein the second line module issues a second alert, and
wherein failure of a crystal in the remote reference clock is detected based on the first alert and the second alert.

### Claim 8

A non-transitory computer readable medium (CRM) comprising instructions stored thereon for reducing a frequency error, the instructions when executed by a processor causes the processor to:
apply a plurality of dither values to a local reference clock over a first time interval by:
applying, by modifying a divider, a first set of positive dither values during a first half of the first time interval, and
applying, by modifying the divider, a second set of negative dither values during a second half of the first time interval;
track a plurality of bit errors from sampling a first plurality of data values received over an asynchronous link,
wherein the first plurality of data values are sampled during the first time interval using the local clock reference, and
wherein the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; and
adjust, based on the plurality of bit errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

### Claim 9 (depends on 8)

The non-transitory CRM of claim 8, wherein the first set of positive dither values has a maximum dither value of 1.0 parts per million (PPM), and wherein two consecutive positive dither values have a step size of 100 parts per billion (PPB).

### Claim 10 (depends on 8)

The non-transitory CRM of claim 8, wherein the application of the first set of positive dither values comprises:
modifying a numerator in the divider in a clock synthesizer integrated circuit of the local reference clock.

### Claim 11 (depends on 8)

The non-transitory CRM of claim 8, wherein the tracking of the plurality of bit errors comprises:
counting a first number of bit errors during the first half of the first time interval;
counting a second number of bit errors during the second half of the first time interval; and
generating a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the adjusting of the frequency of the local reference clock is based on the comparison.

### Claim 12 (depends on 8)

The non-transitory CRM of claim 8, further comprising instructions when executed by the processor causes the processor to:
apply, after adjusting the frequency of the local reference clock, the first set of positive dither values to the local reference clock during a first half of a second time interval;
apply, after adjusting the local reference clock, the second set of negative dither values to the local reference clock during a second half of the second time interval;
sample, during the second time interval and using the local reference clock, a second plurality of data values received over the asynchronous link, wherein the second plurality of data values are transmitted over the asynchronous link based on the remote reference clock;
count a first number of bit errors from the sampling of the second plurality of data values during the first half of the second time interval;
count a second number of bit errors from the sampling of the second plurality of data values during the second half; and
generate a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein the comparison indicates that the first number of bit errors and the second number of bit errors are balanced.

### Claim 13

A system for reducing a frequency error, comprising:
a local reference clock comprising a divider;
a clock and data recovery (CDR) circuit configured to sample, using the local reference clock, a plurality of data values during a first time interval, wherein the first plurality of data values are received over an asynchronous link, and wherein the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; and
an error monitoring and frequency control (EMFC) circuit configured to:
apply a plurality of dither values to the local reference clock over the first time interval by:
applying, by modifying the divider, a first set of positive dither values during a first half of the first time interval, and
applying, by modifying the divider, a second set of negative dither values during a second half of the first time interval,
track a plurality of bit errors from the sampling of the first plurality of data values, and
adjust, based on the plurality of bit errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.

### Claim 14 (depends on 13)

The system of claim 13, further comprising:
a forward error correction (FEC) circuit connected to both the CDR circuit and the EMFC circuit and configured to detect the plurality of bit errors.

### Claim 15 (depends on 14)

The system of claim 14, wherein:
the local reference clock comprises a clock synthesizer integrated circuit comprising the divider; and
the EMFC circuit applies the plurality of dither values by modifying a numerator of the divider.

### Claim 16 (depends on 15)

The system of claim 15, wherein:
the tracking of the plurality of bit errors comprises:
counting a first number of bit errors during the first half, counting a second number of bit errors during the second half, and generating a comparison by comparing the first number of bit errors with the second number of bit errors,
wherein adjusting the frequency of the local reference clock is based on the comparison.

### Claim 17 (depends on 13)

The system of claim 13, wherein the local reference clock, the CDR circuit, and the EMFC circuit are located in a first line module of a telecommunications system, and wherein the remote reference clock is located in a switch module of the telecommunications system connected to the first line module and a second line module.

### Claim 18 (depends on 17)

The system of claim 17, wherein:
the first line module issues a first alert based on repeated adjustments to the local reference clock,
the second line module issues a second alert, and
failure of a crystal in the remote reference clock is detected based on the first alert and the second alert.