# US 9,520,906 B2 · Switched capacitor transmitter circuits and methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,906 B2 - Document ID: US9520906B2 - Status: Granted - Kind: B2 - Application number: 14/681,008 - Filed: 2015-04-07 - Published: 2015-12-31 - Granted: 2016-12-13 - Earliest claimed: 2014-06-25 - Applicants: QUALCOMM Incorporated - Inventors: Daniel Keyes Butterfield; Peiyuan Wang; Jeremy Darren Dunworth - Web page: https://patentgrep.com/patent/US9520906B2 ## CPC - H04B 1/0458: {Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages (matching circuits in general H03H)} - H03F 1/02: Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation - H03F 1/0205: {in transistor amplifiers} - H03F 1/32: Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34) - H03F 3/005: {using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence)} - H03F 3/19: with semiconductor devices only - H03F 3/21: with semiconductor devices only {(H03F3/245 takes precedence)} - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03F 3/24: of transmitter output stages - H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)} - H03M 1/066: {by continuously permuting the elements used, i.e. dynamic element matching} - H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) - H03M 7/165: {Conversion to or from thermometric code} - H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)} - H04L 27/3416: {in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes} - H04L 27/36: Modulator circuits; Transmitter circuits - H03F 2200/331: Sigma delta modulation being used in an amplifying circuit - H03F 2200/336: A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/516: Some amplifier stages of an amplifier use supply voltages of different value - H03F 2200/537: A transformer being used as coupling element between two amplifying stages - H03F 2200/541: Transformer coupled at the output of an amplifier - H03F 2203/21142: Output signals of a plurality of power amplifiers are parallel combined to a common output - H03F 2203/45364: the AAC comprising multiple transistors parallel coupled at their gates and sources only, e.g. in a cascode dif amp, only those forming the composite common source transistor - H03M 1/804: {with charge redistribution} - H04B 2001/045: {with means for improving efficiency} - H04B: TRANSMISSION - H03F: AMPLIFIERS - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit. In another embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output. ## Claims ### Claim 1 A transmitter comprising: a switched capacitor transmitter circuit comprising a plurality of capacitors, wherein the plurality of capacitors are switchably coupled between a power supply terminal and a reference voltage terminal; and a thermometer encoder circuit to receive a cartesian modulated signal and produce a positive thermo-encoded signal and a negative thermo-encoded signal, wherein bit lines of the positive thermo-encoded signal are coupled to control particular capacitors of the plurality of capacitors, and wherein bit lines of the negative thermo-encoded signal are coupled to control particular capacitors of the plurality of capacitors in a reversed bit order relative to the bit lines of the positive encoded signal. ### Claim 2 (depends on 1) The transmitter of claim 1 wherein the bit lines of the positive thermo-encoded signal comprise N positive thermo-encoded bits and the bit lines of the negative thermo-encoded signal comprise N bits that are the inverse of the N positive thermo-encoded bits, wherein an nth bit of the positive thermo-encoded signal is coupled to control an nth capacitor of the plurality of capacitors, where n is less than or equal to N, and wherein an nth bit of the negative thermo-encoded signal is coupled to control an N-(n−1)th capacitor of the plurality of capacitors. ### Claim 3 (depends on 1) The transmitter of claim 1 wherein the switched capacitor transmitter circuit further comprises a plurality of switching logic circuits to control switches coupled to the plurality of capacitors, wherein the switching logic circuits receive particular bit lines of the positive thermo-encoded signal and particular bit lines of the negative thermo-encoded signal in said reverse bit order. ### Claim 4 (depends on 3) The transmitter of claim 3 wherein each capacitor in the switched capacitor transmitter circuit comprises a first terminal and a second terminal, wherein the first terminal is coupled to the power supply terminal through a first switch and the first terminal is coupled to the reference voltage terminal through a second switch, wherein the first switch and the second switch are controlled by a particular switching logic circuit, and wherein the second terminal of each capacitor in the plurality of capacitors is coupled to a first node. ### Claim 5 (depends on 3) The transmitter of claim 3 wherein each switching logic circuit combines the positive thermo-encoded signal with a clock signal having a frequency least two times the frequency of the positive thermo-encoded signal and combines the negative thermo-encoded signal with an inverse of said clock signal having a frequency least two times the frequency of the negative thermo-encoded signal. ### Claim 6 (depends on 1) The transmitter of claim 1 further comprising a pseudo differential encoder having an input to receive the cartesian modulated signal, and wherein the thermometer encoder circuit comprises first and second thermometer encoder circuits having inputs coupled to the pseudo differential encoder, wherein the first thermometer encoder circuit receives a positive pseudo-differential encoded component of the cartesian modulated signal and the second thermometer encoder circuit receives a negative pseudo-differential encoded component of the cartesian modulated signal. ### Claim 7 (depends on 1) The transmitter of claim 1 further comprising a delta-sigma modulator having an input to receive the cartesian modulated signal and an output coupled to the thermometer encoder circuit, wherein the thermometer encoder circuit receives the cartesian modulated signal in delta-sigma modulated form. ### Claim 8 (depends on 1) The transmitter of claim 1 wherein the cartesian modulated signal comprises one or more of an in-phase (I) signal and a quadrature (Q) signal. ### Claim 9 (depends on 1) The transmitter of claim 1 wherein the cartesian modulated signal comprises a digitally combined in-phase (I) component and a quadrature (Q) component. ### Claim 10 A method comprising: thermometer encoding a cartesian modulated signal to produce a positive thermo-encoded signal and a negative thermo-encoded signal; and switchably coupling a plurality of capacitors between a power supply terminal and a reference voltage terminal based on the positive thermo-encoded signal and the negative thermo-encoded signal, wherein bit lines of the positive thermo-encoded signal are coupled to control particular capacitors of the plurality of capacitors, and wherein bit lines of the negative thermo-encoded signal are coupled to control particular capacitors of the plurality of capacitors in a reversed bit order relative to the bit lines of the positive encoded signal. ### Claim 11 (depends on 10) The method of claim 10 wherein the bit lines of the positive thermo-encoded signal comprise N positive thermo-encoded bits and the bit lines of the negative thermo-encoded signal comprise N bits that are the inverse of the N positive thermo-encoded bits, wherein an nth bit of the positive thermo-encoded signal is coupled to control an nth capacitor of the plurality of capacitors, where n is less than or equal to N, and wherein an nth bit of the negative thermo-encoded signal is coupled to control an N-(n−1)th capacitor of the plurality of capacitors. ### Claim 12 (depends on 10) The method of claim 10 wherein the plurality of capacitors are controlled by a plurality of switching logic circuits, wherein the particular switching logic circuits receive particular bit lines of the positive thermo-encoded signal and particular bit lines of the negative thermo-encoded signal in said reverse bit order. ### Claim 13 (depends on 12) The method of claim 12 wherein each capacitor comprises a first terminal and a second terminal, wherein the first terminal is coupled to the power supply terminal through a first switch and the first terminal is coupled to the reference voltage terminal through a second switch, wherein the first switch and the second switch are controlled by particular switching logic circuits of the plurality of logic circuits, and wherein the second terminal of each capacitor in the plurality of capacitors is coupled to a first node. ### Claim 14 (depends on 12) The method of claim 12 wherein each switching logic circuit combines the positive thermo-encoded signal with a clock signal having a frequency least two times the frequency of the positive thermo-encoded signal and combines the negative thermo-encoded signal with an inverse of said clock signal having a frequency least two times the frequency of the negative thermo-encoded signal. ### Claim 15 (depends on 10) The method of claim 10 further comprising pseudo differentially encoding the cartesian modulated signal prior to said thermometer encoding. ### Claim 16 (depends on 10) The method of claim 10 further comprising delta-sigma modulating the cartesian modulated signal prior to said thermometer encoding. ### Claim 17 A transmitter comprising: a switched capacitor transmitter circuit comprising a plurality of capacitors, wherein the plurality of capacitors are switchably coupled between a power supply terminal and a reference voltage terminal; a pseudo-differential encoder to receive a cartesian modulated signal and produce a positive pseudo-differential signal and a negative pseudo-differential signal; a first thermometer encoder circuit to receive the positive pseudo-differential signal and produce a positive thermo-encoded signal; and a second thermometer encoder circuit to receive the negative pseudo-differential signal and produce a negative thermo-encoded signal; wherein bit lines of the positive thermo-encoded signal are coupled to control particular capacitors of the plurality of capacitors, and wherein bit lines of the negative thermo-encoded signal are coupled to control particular capacitors of the plurality of capacitors, wherein bit lines of the negative thermo-encoded signal are coupled to control particular capacitors of the plurality of capacitors in a reversed bit order relative to the bit lines of the positive encoded signal. ### Claim 18 (depends on 17) The transmitter of claim 17 wherein the switched capacitor transmitter circuit further comprises a plurality of switching logic circuits to control switches coupled to the plurality of capacitors, wherein the switching logic circuits receive particular bit lines of the positive thermo-encoded signal and particular bit lines of the negative thermo-encoded signal. ### Claim 19 (depends on 17) The transmitter of claim 17 wherein each capacitor in the switched capacitor transmitter circuit comprises a first terminal and a second terminal, wherein the first terminal is coupled to the power supply terminal through a first switch and the first terminal is coupled to the reference voltage terminal through a second switch, wherein the first switch and the second switch are controlled by a particular switching logic circuit, and wherein the second terminal of each capacitor in the plurality of capacitors is coupled to a first node.