# US 9,520,901 B2 · Memory controller, memory system, and memory control method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,901 B2 - Document ID: US9520901B2 - Status: Granted - Kind: B2 - Application number: 14/446,463 - Filed: 2014-07-30 - Published: 2015-09-10 - Granted: 2016-12-13 - Earliest claimed: 2014-03-06 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Riki Suzuki; Toshikatsu Hida; Osamu Torii; Hiroshi Yao; Kiyotaka Iwasaki - Web page: https://patentgrep.com/patent/US9520901B2 ## CPC - H03M 13/35: Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/064: {Management of blocks} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)} - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - H03M 13/29: combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes - H03M 13/2906: {using block codes (H03M13/2957 takes precedence)} - H03M 13/2957: {Turbo codes and decoding} - G11B 20/1833: {by adding special lists or symbols to the coded information (G11B20/1806, G11B20/1866 take precedence)} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 2029/0411: {Online error correction} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R) ## Abstract According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount. ## Claims ### Claim 1 A memory controller that controls a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, comprising: a writing destination management circuit configured to determine a writing destination of user data in the nonvolatile memory; an encoding circuit configured to encode the user data to generate a parity, the encoding circuit performing the encoding according to a plurality of encoding methods having different error correction capabilities, the plurality of encoding methods including a first encoding method and a second encoding method of which the error correction capability is higher than that of the first encoding method; a decoding circuit configured to decode the user data and the parity which are read out of the nonvolatile memory, the decoding circuit detecting a number of errors in the user data; a writing control circuit configured to control the nonvolatile memory to write the user data at the writing destination determined by the writing destination management circuit; and an Error Correcting Code (ECC) management circuit configured to obtain the number of errors in the user data of each of the plurality of memory areas, to select an encoding method among the plurality of encoding methods to be performed on user data which is stored in a first memory area among the plurality of memory areas, and to instruct the encoding circuit to encode the user data according to the encoding method corresponding to the first memory area, the first memory area corresponding to the writing destination of the user data, wherein the ECC management circuit changes the encoding method corresponding to the first memory area from the first encoding method to the second encoding method when the number of errors in the user data of the first memory area is equal to or higher than a threshold and a total sum of parities of the nonvolatile memory is equal to or less than a predetermined amount, wherein a predetermined size of parity is generated for a first size of the user data when the encoding is performed according to the first encoding method, and the predetermined size of the parity is generated for a second size of the user data smaller than the first size when the encoding is performed according to the second encoding method. ### Claim 2 (depends on 1) The memory controller according to claim 1, wherein each of the plurality of memory areas is a page. ### Claim 3 (depends on 1) The memory controller according to claim 1, wherein each of the plurality of memory areas is a block. ### Claim 4 (depends on 1) The memory controller according to claim 1, wherein each of the plurality of memory areas is a memory chip. ### Claim 5 (depends on 1) The memory controller according to claim 1, wherein each of the plurality of memory areas is an area being simultaneously read out. ### Claim 6 (depends on 1) The memory controller according to claim 1, wherein the nonvolatile memory is configured to be simultaneously written in a plurality of blocks, and be simultaneously read data out of the plurality of blocks, and each of the plurality of memory areas is the plurality of blocks. ### Claim 7 (depends on 1) The memory controller according to claim 1, wherein the writing destination management circuit determines a writing destination in units of clusters of a certain size for the user data, and determines a writing destination of a code word configured by a cluster and parity corresponding to the cluster as a memory area of the nonvolatile memory which is simultaneously read out. ### Claim 8 (depends on 7) The memory controller according to claim 7, wherein the number of code words, in each encoding method, which are stored in each of the plurality of memory areas being simultaneously read out is an integer. ### Claim 9 (depends on 7) The memory controller according to claim 7, wherein the cluster is larger than a minimum unit of user data which is managed by a host. ### Claim 10 A memory controller that controls a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, comprising: a writing destination management circuit configured to determine a writing destination of user data in the nonvolatile memory; an encoding circuit configured to encode the user data to generate a parity, the encoding circuit performing the encoding according to a plurality of encoding methods having different error correction capabilities, the plurality of encoding methods including a first encoding method and a second encoding method of which the error correction capability is higher than that of the first encoding method; an Error Correcting Code (ECC) management circuit configured to measure write frequency of each of the plurality of memory areas, to select an encoding method among the plurality of encoding methods to be performed on user data which is stored in a first memory area among the plurality of memory areas, and to instruct the encoding circuit to encode the user data according to the encoding method corresponding to the first memory area, the first memory area corresponding to the writing destination of the user data; and a writing control circuit configured to control the nonvolatile memory to write the user data at the writing destination determined by the writing destination management circuit, wherein the ECC management circuit changes the encoding method corresponding to the first memory area from the first encoding method to the second encoding method when the write frequency of the first memory area is equal to or higher than a threshold and a total sum of parities of the nonvolatile memory is equal to or less than a predetermined amount, wherein a predetermined size of parity is generated for a first size of the user data when the encoding is performed according to the first encoding method, and the predetermined size of parity is generated for a second size of the user data smaller than the first size when the encoding is performed according to the second encoding method. ### Claim 11 (depends on 10) The memory controller according to claim 10, wherein each of the plurality of memory areas is a page. ### Claim 12 (depends on 10) The memory controller according to claim 10, wherein each of the plurality of memory areas is a block. ### Claim 13 (depends on 10) The memory controller according to claim 10, wherein each of the plurality of memory areas is a memory chip. ### Claim 14 (depends on 10) The memory controller according to claim 10, wherein each of the plurality of memory areas is an area being simultaneously read out. ### Claim 15 (depends on 10) The memory controller according to claim 10, wherein the nonvolatile memory is configured to be simultaneously written in a plurality of blocks, and be simultaneously read data out of the plurality of blocks, and each of the plurality of memory areas is the plurality of blocks. ### Claim 16 A memory controller that controls a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, comprising: a writing destination management circuit configured to determine a writing destination of user data in the nonvolatile memory; an encoding circuit configured to encode the user data to generate a parity, the encoding circuit performing the encoding according to a plurality of encoding methods having different error correction capabilities, the plurality of encoding methods including a first encoding method and a second encoding method of which the error correction capability is higher than that of the first encoding method; an Error Correcting Code (ECC) management circuit configured to measure erase frequency of each of the plurality of memory areas, to select an encoding method among the plurality of encoding methods to be performed on user data which is stored in a first memory area among the plurality of memory areas, and to instruct the encoding circuit to encode the user data according to the encoding method corresponding to the first memory area, the first memory area corresponding to the writing destination of the user data; and a writing control circuit configured to control the nonvolatile memory to write the user data at the writing destination determined by the writing destination management circuit, wherein the ECC management circuit changes the encoding method corresponding to the first memory area from the first encoding method to the second encoding method when the erase frequency of the first memory area is equal to or higher than a threshold and a total sum of parities of the nonvolatile memory is equal to or less than a predetermined amount, wherein a predetermined size of parity is generated for a first size of the user data when the encoding is performed according to the first encoding method, and the predetermined size of parity is generated for a second size of the user data smaller than the first size when the encoding is performed according to the second encoding method. ### Claim 17 (depends on 16) The memory controller according to claim 16, wherein each of the plurality of memory areas is a page. ### Claim 18 (depends on 16) The memory controller according to claim 16, wherein each of the plurality of memory areas is a block. ### Claim 19 (depends on 16) The memory controller according to claim 16, wherein each of the plurality of memory areas is a memory chip. ### Claim 20 (depends on 16) The memory controller according to claim 16, wherein each of the plurality of memory areas is an area being simultaneously read out.