# US 9,520,895 B2 · Low power analog to digital converter

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- Number: US 9,520,895 B2
- Document ID: US9520895B2
- Status: Granted
- Kind: B2
- Application number: 14/705,805
- Filed: 2015-05-06
- Published: 2016-08-11
- Granted: 2016-12-13
- Earliest claimed: 2012-12-19
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Takao Oshita; George L. Geannopoulos; David E. Duarte; J Keith Hodgson; James S. Ayers; Avner Kornfeld; Jonathan P. Douglas
- Web page: https://patentgrep.com/patent/US9520895B2

## CPC

- H03M 3/458: {Analogue/digital converters using delta-sigma modulation as an intermediate step}
- H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed}
- H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters}
- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 3/32: {with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed}
- H03M 3/34: {by chopping}
- H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00)
- H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence)
- H03M 1/804: {with charge redistribution}
- H03M 3/30: {Delta-sigma modulation}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

## Claims

### Claim 1

An apparatus comprising:
at least two analog multiplexers;
at least two analog to digital converters (ADC) to receive outputs of the at least two analog multiplexers and to generate corresponding at least two digital outputs; and
a digital multiplexer to receive the at least two digital outputs, and to selectively provide a logic output according to one of the selected at least two digital outputs.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein at least one of the at least two ADCs comprises a sigma-delta modulator.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the sigma-delta modulator comprises:
a first capacitor; and
at least two switches, one of which is operable to couple an input analog signal to the first capacitor, and the other switch is operable to couple a reference signal or a logic signal to the first capacitor.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the sigma-delta modulator comprises:
an integrator having an input coupled to the first capacitor;
a multiplexer operable to select an output of the integrator or an inverse of the output of the integrator; and
a sampler to sample the output of the multiplexer.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein an output of the sampler is one of the at least two digital outputs, and wherein the output of the sampler is used to select one of the reference signal or the logic signal for coupling to the other switch.

### Claim 6 (depends on 4)

The apparatus of claim 4, wherein the integrator comprises:
an amplifier having an input coupled to the first capacitor;
a first switch coupled to the input of the amplifier and an output of the amplifier;
a second capacitor coupled to the output of the amplifier; and
a second switch coupled to the second capacitor and the input of the amplifier.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the amplifier is one of:
a cascode inverter amplifier;
an inverter, or
an operational amplifier.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the first and second switches are controllable by two different phases of a clock signal.

### Claim 9 (depends on 3)

The apparatus of claim 3, wherein the first capacitor is a switched capacitor subtractor.

### Claim 10 (depends on 1)

The apparatus of claim 1 comprises a counter to count a number of ones or zeros in the logic output to generate a digital code.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein each of the at least two analog multiplexers is controllable by a separate select line.

### Claim 12

A method comprising:
coupling an input analog signal to a first capacitor during a first phase of a clock signal;
closing a first switch of an integrator during the first phase such that an input and an output of an amplifier of the integrator are electrically shorted;
coupling one of a reference signal or a logic signal to the first capacitor during a second phase of the clock signal; and
closing a second switch of the integrator during the second phase, the second switch to couple the input and the output of the amplifier via a second capacitor.

### Claim 13 (depends on 12)

The method of claim 12, comprises:
controlling a third switch using the first phase, the third switch to couple one of the reference signal or the logic signal to the first capacitor during a chopping mode; and
controlling a fourth switch using the second phase, the fourth switch to couple the input analog signal to the first capacitor during the chopping mode.

### Claim 14 (depends on 12)

The method of claim 12, wherein coupling one of the reference signal or the logic signal to the first capacitor is according to a logic state of the output of the amplifier.

### Claim 15

An apparatus comprises:
a first analog to digital converter (ADC) including:
a first capacitor; and
at least two switches, one of which is operable to couple an input analog signal to the first capacitor of the first ADC, and the other switch is operable to couple a first reference signal or a first logic signal to the first capacitor of the first ADC; and
a second ADC including:
a first capacitor; and
at least two switches, one of which is operable to couple the input analog signal to the first capacitor of the second ADC, and the other switch is operable to couple a second reference signal or a second logic signal to the first capacitor of the second ADC.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein one of the switches of the first ADC, which is operable to couple the input analog signal to the first capacitor of the first ADC, is controllable by a first phase of a clock signal, and wherein one of the switches of the second ADC, which is operable to couple the input analog signal to the first capacitor of the second ADC, is controllable by a second phase of the clock signal.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the other switch of the first ADC, which is operable to couple the first reference signal or the first logic signal to the first capacitor of the first ADC, is controllable by the second phase, and wherein the switch of the second ADC, which is operable to couple the second reference signal or the second logic signal to the first capacitor of the second ADC, is controllable by the first phase.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein each of the first and second ADCs include:
an integrator having an input coupled to the first capacitor of the respective ADC;
a multiplexer operable to select an output of the integrator or an inverse of the output of the integrator; and
a sampler to sample the output of the multiplexer.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the integrator comprises:
an amplifier having an input coupled to the first capacitor;
a first switch coupled to the input of the amplifier and an output of the amplifier;
a second capacitor coupled to the output of the amplifier; and
a second switch coupled to the second capacitor and the input of the amplifier.

### Claim 20 (depends on 15)

The apparatus of claim 15, wherein the first capacitors of the first and second ADCs are switched capacitor subtractors, respectively.