# US 9,520,893 B1 · Architecture for ensuring monotonicity in a digital-to-analog converter

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,893 B1
- Document ID: US9520893B1
- Status: Granted
- Kind: B1
- Application number: 15/067,500
- Filed: 2016-03-11
- Granted: 2016-12-13
- Earliest claimed: 2016-03-11
- Assignees: Avnera Corporation
- Applicants: Avnera Corporation
- Inventors: Christopher D. Nilson
- Web page: https://patentgrep.com/patent/US9520893B1

## CPC

- H03M 1/747: {with equal currents which are switched by unary decoded digital signals}
- G05F 3/262: {using field-effect transistors only}
- H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00)
- H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence)
- H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j−1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.

## Claims

### Claim 1

A binary divider circuit having K bits, the divider circuit comprising:
a current mirror having a first transistor and a second transistor, each transistor having a source, the source of the first transistor being electrically connected to the source of the second transistor, the first transistor having a programmable gain N, where N is greater than or equal to 1, the second transistor having a programmable gain M, where the sum of N plus M equals 2K, where K is the number of bits in the divider circuit; and
a current source electrically connected to the source of the first transistor and the source of the second transistor, the current source configured to produce a current I0.

### Claim 2 (depends on 1)

The divider circuit of claim 1, the first transistor and the second transistor each further having a gate and a drain, in which the gate of the first transistor is electrically connected to the gate of the second transistor, and in which the gate of the first transistor and the gate of the second transistor are electrically connected to the drain of the first transistor.

### Claim 3 (depends on 1)

The divider circuit of claim 1, in which the current source is connected to the source of the first transistor and the source of the second transistor at a node of the current source, and in which the current source is further connected to ground at another node of the current source.

### Claim 4

A digital-to-analog converter (DAC) configured to convert a digital word input having J bits to an analog signal, the DAC comprising:
2J current sources, in which each of the 2J current sources is configured to produce a current having a value I0;
an output node;
a current divider having a programmable divide ratio, D, where 1/D is between 0 and 1;
a first switch configured to selectively couple 2J−1 of the 2J current sources to the output node, in which one of the 2J current sources is not coupled to the output node; and
a second switch configured to selectively couple each of the 2J current sources to the current divider.

### Claim 5 (depends on 4)

The DAC of claim 4, in which the programmable divide ratio is M/(N+M), where N is greater than or equal to 1 and M=2K−N.

### Claim 6 (depends on 4)

The DAC of claim 4, in which the current divider has K bits and includes a current mirror, the current mirror further having a first transistor and a second transistor, each transistor having a source, the source of the first transistor being electrically coupled to the source of the second transistor, the first transistor having a programmable gain N, where N is greater than or equal to 1, the second transistor having a programmable gain M, where M=2K−N.

### Claim 7 (depends on 6)

The DAC of claim 6, in which the source of the first transistor and the source of the second transistor define a common source, in which the first transistor and the second transistor each further have a gate and a drain, in which the gate of the first transistor is electrically coupled to the gate of the second transistor, in which the gate of the first transistor and the gate of the second transistor are electrically coupled to the drain of the first transistor, and in which the current mirror is configured to have a current gain M/(N+M) from the common source of the first transistor and the second transistor to the drain of the second transistor.

### Claim 8 (depends on 4)

The DAC of claim 4, further comprising a power supply electrically coupled to the drain of the first transistor.

### Claim 9 (depends on 8)

The DAC of claim 8, in which the power supply is coupled to the drain of the first transistor through a third transistor.

### Claim 10

A method of dividing a current with a programmable current mirror having K bits, the method comprising:
coupling a current source, producing a current, I0, to the current mirror, the current mirror having a first transistor and a second transistor, each transistor having a source, the source of the first transistor being electrically coupled to the source of the second transistor, the first transistor having a programmable gain, the second transistor having a programmable gain;
configuring the programmable gain of the first transistor to a value N, where N is greater than or equal to 1;
configuring the programmable gain of the second transistor to a value M, where M=2K−N; and
outputting a divided current from the programmable current mirror, the divided current being I0×(M/(N+M)).

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
reconfiguring the programmable gain of the first transistor to a value Nnew, where Nnew is greater than or equal to 1 and Nnew does not equal N; and
reconfiguring the programmable gain of the second transistor to a value Mnew, where Mnew=2K−Nnew and Mnew does not equal M.

### Claim 12 (depends on 11)

The method of claim 11, further comprising iteratively reconfiguring the programmable gain of the first transistor and iteratively reconfiguring the programmable gain of the second transistor, for a plurality of values of Nnew and Mnew where Mnew+Nnew=2K.

### Claim 13

A method of dividing a current within a digital-to-analog converter (DAC) configured to convert a digital word input having J bits to an analog signal, the method comprising:
selectively coupling each of 2J current sources to an input side of a current divider, an output side of the current divider being coupled to an output node of the DAC, each of the 2J current sources producing a current having a value I0, the current divider having a programmable divide ratio, D, where 1/D is between 0 and 1; and
selectively coupling 2J−1 of the 2J current sources to the output node of the DAC, in which one of the 2J current sources is not coupled to the output node.

### Claim 14 (depends on 13)

The method of claim 13, further comprising iteratively reconfiguring the current divider to have another programmable divide ratio, Dnew, where 1/Dnew is between 0 and 1 and Dnew does not equal D, before:
again selectively coupling each of 2J current sources to the input side of the current divider; and
again selectively coupling 2J−1 of the 2J current sources to the output node of the DAC, in which one of the 2J current sources is not coupled to the output node.

### Claim 15 (depends on 13)

The method of claim 13, in which the programmable divide ratio, D, is M/(N+M), where N is greater than or equal to 1 and M=2K−N.

### Claim 16 (depends on 15)

The method of claim 15, further comprising reconfiguring the current divider to have another programmable divide ratio Mnew/(Nnew+Mnew), where Nnew is greater than or equal to 1, Nnew does not equal N, and Mnew=2K−Nnew, before:
again selectively coupling each of 2J current sources to the input side of the current divider; and
again selectively coupling 2J−1 of the 2J current sources to the output node of the DAC, in which one of the 2J current sources is not coupled to the output node.

### Claim 17 (depends on 16)

The method of claim 16, further comprising iteratively reconfiguring the current divider for a plurality of values of Nnew and Mnew where Mnew+Nnew=2K.

### Claim 18 (depends on 13)

The method of claim 13, in which the current divider includes a first transistor having a programmable gain of N, where N is greater than or equal to 1, and a second transistor having a programmable gain of M, where M=2K−N, the method further comprising outputting a divided current from the current divider, the divided current being I0×(M/(N+M)).

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
reconfiguring the programmable gain of the first transistor to a value Nnew, where Nnew is greater than or equal to 1 and Nnew does not equal N;
reconfiguring the programmable gain of the second transistor to a value Mnew, where Mnew=2K−Nnew and Mnew does not equal M; and
outputting a new divided current from the current divider, the new divided current being I0×(Mnew/(Nnew+Mnew)).

### Claim 20 (depends on 19)

The method of claim 19, further comprising iteratively reconfiguring the programmable gain of the first transistor and iteratively reconfiguring the programmable gain of the second transistor, for a plurality of values of Nnew and Mnew where Mnew+Nnew=2K.