# US 9,520,892 B2 · Digital to analog converter, unit for the same, and method for using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,892 B2 - Document ID: US9520892B2 - Status: Granted - Kind: B2 - Application number: 14/979,521 - Filed: 2015-12-28 - Published: 2016-06-30 - Granted: 2016-12-13 - Earliest claimed: 2014-12-29 - Assignees: Gwangju Institute of Science and Technology - Applicants: Gwangju Institute of Science and Technology - Inventors: Min-Jae Lee; Seong-Geon Kim; Jae-Hyun Kang - Web page: https://patentgrep.com/patent/US9520892B2 ## CPC - H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) - H03K 3/356121: {with synchronous operation (H03K3/35613, H03K3/356147 take precedence)} - H03K 5/14: by the use of delay lines (H03K5/133 takes precedence) - H03M 1/0607: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295)} - H03M 1/0863: {of switching transients, e.g. glitches} - H03M 1/74: Simultaneous conversion - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Disclosed herein is a digital-to-analog converter (DAC) including a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value. According to the present invention, distortion of the output of the DAC may be attenuated and loss of the output may be minimized by utilizing the RZ technique. ## Claims ### Claim 1 A digital-to-analog converter (DAC) comprising: a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value. ### Claim 2 (depends on 1) The DAC according to claim 1, wherein the clock driver adjusts enablement and disablement of RZ. ### Claim 3 (depends on 1) The DAC according to claim 1, wherein the DAC core comprises: an RZ flip-flop for outputting 0 as a flip-flop output signal and an inverse flip-flop output signal such that the RZ section is established when both the clock signal and the inverse delay clock signal are 1; a switch driver for outputting 0 as a reset signal when both the flip-flop output signal and the inverse flip-flop output signal are 0; and an output unit comprising an RZ signal switch unit and an output signal switch unit, the RZ signal switch unit setting an output value to 0 in a section having the reset signal equal to 0 and the output signal switch unit providing a positive or negative output value in a section having the reset signal unequal to 0. ### Claim 4 (depends on 1) The DAC according to claim 1, wherein the RZ section is adjusted by a signal constituted in 4 bits. ### Claim 5 (depends on 1) The DAC according to claim 1, wherein the digital input value is obtained by converting an original digital input value through a dynamic element matching (DEM) circuit, wherein the DEM circuit is adjustable to be turned on and off. ### Claim 6 A digital-to-analog converter (DAC) unit comprising: a return to zero (RZ) flip-flop for receiving a clock signal and an inverse delay clock signal delayed by an RZ section by converting the clock signal and outputting 0 as a flip-flop output signal and an inverse flip-flop output signal in the RZ section; a switch driver for outputting 0 as a reset signal when both the flip-flop output signal and the inverse flip-flop output signal are 0; and an output unit for outputting an output value of 0 in a section having the reset signal equal to 0 and outputting a positive or negative output value in a section having the reset signal unequal to 0. ### Claim 7 (depends on 6) The DAC unit according to claim 6, wherein the RZ flip-flop is configured as hardware. ### Claim 8 (depends on 7) The DAC unit according to claim 7, wherein the RZ flip-flop comprises: a sense amplifier for outputting, when the clock signal corresponds to a rising edge, logic values of a digital input value and an inverse digital input value as a reset set signal and a sensing set signal and maintaining the logic values until a rising edge of a next clock signal appears; and an RZ latch for outputting 0 as the flip-flop output signal and the inverse flip-flop output signal when the clock signal and the inverse delay clock signal are 1, and outputting, when any one of the clock signal and the inverse delay clock signal is not 1,the flip-flop output signal and the inverse flip-flop output signal such that the flip-flop output signal complies with a value of the reset set signal, and the inverse flip-flop output signal complies with a value of the sensing set signal. ### Claim 9 (depends on 6) The DAC unit according to claim 6, wherein the switch driver comprises an inverter for inverting the flip-flop output signal and the inverse flip-flop output signal and outputting final switch pair input data and inverse final switch pair input data. ### Claim 10 (depends on 9) The DAC unit according to claim 9, wherein the switch driver comprises: two reset switches having a power supply as a source, having the final switch pair input data and the inverse final switch pair input data as gates thereof, and having a reset signal output terminal for outputting the reset signal connected to a drain. ### Claim 11 (depends on 6) The DAC unit according to claim 6, further comprising: an RZ switch unit for outputting an output value of 0 in a section having the reset signal equal to 0; and an output signal switch unit for outputting a positive or negative output value in a section having the reset signal unequal to 0. ### Claim 12 (depends on 11) The DAC unit according to claim 11, wherein the RZ switch unit and the output signal switch unit are connected in parallel. ### Claim 13 A method of operating a digital-to-analog converter (DAC) comprising a clock driver and a DAC core, the method comprising: controlling, by the clock driver, a clock signal to provide an inverse delay clock signal for allow at least selective adjustment of a return to zero (RZ) section; receiving, by the DAC core comprising at least two DAC units, the clock signal, the inverse delay clock signal, and a digital input value; adjusting, by the DAC core, the RZ section based on the received clock signal and the received inverse delay clock signal; and converting, by the DAC core, the digital input value based on the adjusted RZ section to output an analog output value. ### Claim 14 (depends on 13) The method according to claim 13, wherein the RZ section is adjusted by comparing the clock signal and the inverse delay clock signal. ### Claim 15 (depends on 13) The method according to claim 13, wherein a duration of time when both the clock signal and the inverse delay clock signal are 1 is the RZ section.