# US 9,520,889 B2 · Apparatus and method for combining multiple charge pumps in phase locked loops > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,889 B2 - Document ID: US9520889B2 - Status: Granted - Kind: B2 - Application number: 14/626,663 - Filed: 2015-02-19 - Published: 2016-07-21 - Granted: 2016-12-13 - Earliest claimed: 2015-01-20 - Assignees: Broadcom Corporation - Applicants: Broadcom Corporation - Inventors: Gregory Alyn Unruh - Web page: https://patentgrep.com/patent/US9520889B2 ## CPC - H03L 7/1974: {for fractional frequency division} - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H03K 3/013: Modifications of generator to prevent operation by noise or interference - H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop - H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider} - H04B 1/40: Circuits - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04B: TRANSMISSION ## Abstract A frequency synthesizer includes circuitry configured to generate two or more feedback clocks based on the oscillation signals output from a voltage-controlled oscillator. The circuitry also modulates the feedback clocks based on fractional offsets from a reference clock frequency for input into two or more phase and frequency detectors. Multiple charge pump circuits receive inputs from these phase and frequency detectors. The current from these charge pumps is summed and input to a low pass filter. The output of the filter represents an average of the time difference between the reference clock and the multiple feedback clocks. ## Claims ### Claim 1 A frequency synthesizer comprising: circuitry configured to generate two or more feedback clocks based on oscillation signals output from a voltage-controlled oscillator; modulate the two or more feedback clocks based on fractional offsets from a reference clock frequency for input into a plurality of phase and frequency detectors (PFDs) driving a plurality of charge pumps; and select an output from one of the plurality of PFDs corresponding to an early feedback clock input that leads a reference clock or a late feedback clock input that lags the reference clock to drive each of the plurality of charge pumps, wherein the circuitry is further configured to randomize selections of the plurality of charge pumps associated with the early feedback clock and late feedback clock. ### Claim 2 (depends on 1) The frequency synthesizer of claim 1, wherein the circuitry is further configured to select the early feedback clock or the late feedback clock to drive the plurality of charge pumps based on a calculated phase residue output from a sigma-delta modulator. ### Claim 3 (depends on 1) The frequency synthesizer of claim 1, wherein a net charge of the currents output from the plurality of charge pumps is equal to zero. ### Claim 4 (depends on 1) The frequency synthesizer of claim 1, wherein an amount of fractional offset corresponds to a quantity of charge pumps; and the circuitry is configured to incrementally step through one or more phases of the early feedback clock and the late feedback clock at a rate based on the amount of fractional offset. ### Claim 5 (depends on 4) The frequency synthesizer of claim 4, wherein the amount of fractional offset is equal to 1/16 and quantity of charge pumps is equal to sixteen. ### Claim 6 (depends on 1) The frequency synthesizer of claim 1, wherein the circuitry is further configured to modulate an integer part and a fractional part of the fractional offsets. ### Claim 7 (depends on 6) The frequency synthesizer of claim 6, wherein the circuitry is further configured to generate clock edges for the two or more feedback clocks at phases corresponding to the fractional offsets. ### Claim 8 (depends on 7) The frequency synthesizer of claim 7, wherein the circuitry is further configured to modulate between one or more integer values indicating a number of selected charge pumps. ### Claim 9 (depends on 1) The frequency synthesizer of claim 1, wherein the circuitry is further configured to delay one or more of the feedback clocks by a number of the oscillation signals output from the voltage-controlled oscillator. ### Claim 10 (depends on 1) The frequency synthesizer of claim 1, wherein the two or more charge pumps and the two or more phase and frequency detectors operate in linear gain regions. ### Claim 11 (depends on 1) The frequency synthesizer of claim 1, wherein the circuitry is further configured to filter signals output from the plurality of charge pumps based on an amount of phase noise present in the oscillation signals output from the voltage-controlled oscillator. ### Claim 12 (depends on 1) The frequency synthesizer of claim 1, wherein a sum of outputs from the plurality of charge pumps corresponds to a weighted offset between one or more charge pumps driven by the early feedback clock and one or more charge pumps driven by the late feedback clock. ### Claim 13 (depends on 1) The frequency synthesizer of claim 1, wherein the circuitry is further configured to select the early feedback clock or the late feedback clock to drive the plurality of charge pumps based on a predetermined number of additional bits retained in an integer phase output of a sigma-delta modulator indicating a first number of charge pumps driven by the early feedback clock and a second number of charge pumps driven by the late feedback clock. ### Claim 14 (depends on 13) The frequency synthesizer of claim 13, wherein four additional bits are retained in the integer phase output of the sigma-delta modulator to indicate the first number of charge pumps driven by the early feedback clock and the second number of charge pumps driven by the late feedback clock. ### Claim 15 A frequency synthesizer comprising: circuitry configured to generate two or more feedback clocks based on oscillation signals output from a voltage-controlled oscillator; modulate the two or more feedback clocks based on fractional offsets from a reference clock frequency for input into a plurality of phase and frequency detectors (PFDs) driving a plurality of charge pumps; and toggle between an early feedback clock and a late feedback clock driving the plurality of charge pumps based on a feedback clock selector signal. ### Claim 16 (depends on 15) The frequency synthesizer of claim 15, wherein the circuitry is further configured to randomize selection of the early feedback clock and the late feedback clock. ### Claim 17 (depends on 15) The frequency synthesizer of claim 15, wherein the circuitry is further configured to randomize selections of the plurality of charge pumps driven by the early feedback clock or the late feedback clock. ### Claim 18 (depends on 15) The frequency synthesizer of claim 15, wherein the circuitry is further configured to reset outputs of the plurality of PFDs via a delayed feedback clock signal associated with each of the early feedback clock and the late feedback clock. ### Claim 19 A frequency synthesizer comprising: circuitry configured to generate two or more feedback clocks based on oscillation signals output from a voltage-controlled oscillator; modulate the two or more feedback clocks based on fractional offsets from a reference clock frequency for input into a plurality of phase and frequency detectors (PFDs) driving a plurality of charge pumps; and modulate an early feedback clock and a late feedback clock at equal and opposite phase and frequency offsets from a center frequency.