# US 9,520,884 B2 · Phase lock loop with dynamic lock ranges > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,884 B2 - Document ID: US9520884B2 - Status: Granted - Kind: B2 - Application number: 14/811,558 - Filed: 2015-07-28 - Published: 2016-02-04 - Granted: 2016-12-13 - Earliest claimed: 2014-08-01 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Aaron L. Frank; Hamid R. Safiri - Web page: https://patentgrep.com/patent/US9520884B2 ## CPC - H03L 7/099: concerning mainly the controlled oscillator of the loop - H03L 1/023: {by using voltage variable capacitance diodes} - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL device during the calibration process. Based on this temperature reading, the calibration circuit initiates a preset procedure that presets a control voltage of a voltage control oscillator in the PLL device. The preset procedure implements a calibration function defined by a slope with a numerator component and a denominator component. The numerator component corresponds to a range of the control voltage, whereas the denominator component corresponds to a range of ambient temperatures within which the PLL device operates. ## Claims ### Claim 1 A system comprising: a phase lock loop (PLL) circuit including: a voltage control oscillator (VCO) configured to receive a control voltage and generate an adjusted oscillation signal having a target frequency adjustable by the control voltage; a frequency divider coupled with the VCO to receive the adjusted oscillation signal, the frequency divider configured to generate a feedback oscillation signal by reducing the target frequency; and a detector circuit coupled between the frequency divider and the VCO, the detector circuit configured to detect a difference between the feedback oscillation signal and a reference oscillation signal, and configured to generate the control voltage based on the difference; a temperature sensor configured to generate a temperature reading corresponding to a junction temperature of the PLL circuit; and a calibration circuit coupled with the temperature sensor and the detector circuit, the calibration circuit configured to override the detector circuit and preset the control voltage based on the temperature reading during a calibration procedure of the PLL circuit. ### Claim 2 (depends on 1) The system of claim 1, wherein: the calibration circuit is configured to preset the control voltage based on a linear function of the temperature reading; and the linear function is defined by a slope having a numerator corresponding to an output range of the detector circuit. ### Claim 3 (depends on 1) The system of claim 1, wherein: the calibration circuit is configured to preset the control voltage based on a linear function of the temperature reading; and the linear function is defined by a slope having a denominator corresponding to a range of ambient temperatures within which the PLL circuit operates. ### Claim 4 (depends on 1) The system of claim 1, wherein: the calibration circuit is configured to preset the control voltage based on a linear function of the temperature reading; and the linear function includes a constant value defined by a minimum control voltage at a minimum temperature at which the PLL circuit operates. ### Claim 5 (depends on 1) The system of claim 1, wherein: the detector circuit includes an amplifier configured to amplify the detected difference between the feedback oscillation signal and the reference oscillation signal; and the amplifier is configured to generate the control voltage varying within an output range based on the amplified difference. ### Claim 6 (depends on 1) The system of claim 1, wherein: the detector circuit includes an amplifier having an input for receiving the detected difference and an output for delivering the control voltage based on the detected difference; and the calibration circuit is configured to override the detector circuit by redirecting the input of the amplifier to receive the control voltage delivered at the output of the amplifier during only the calibration procedure. ### Claim 7 (depends on 1) The system of claim 1, wherein: the VCO includes a varactor having a variable capacitance tunable by the control voltage for adjusting the target frequency; and the calibration circuit is configured to preset the control voltage to reduce the variable capacitance when the temperature reading is above a predetermined threshold. ### Claim 8 (depends on 1) The system of claim 1, wherein: the VCO includes a varactor having a variable capacitance tunable by the control voltage for adjusting the target frequency; and the calibration circuit is configured to preset the control voltage to increase the variable capacitance when the temperature reading is below a predetermined threshold. ### Claim 9 A phase lock loop (PLL) circuit, comprising: a voltage control oscillator (VCO) configured to receive a control voltage and generate an adjusted oscillation signal having a target frequency adjustable by the control voltage; a frequency divider coupled with the VCO to receive the adjusted oscillation signal, the frequency divider configured to generate a feedback oscillation signal by reducing the target frequency; a detector circuit coupled between the frequency divider and the VCO, the detector circuit configured to detect a difference between the feedback oscillation signal and a reference oscillation signal, and configured to generate the control voltage based on the difference; and a calibration circuit coupled with the detector circuit, the calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL circuit, the calibration circuit configured to preset the control voltage based on the temperature reading during a calibration procedure of the PLL circuit. ### Claim 10 (depends on 9) The PLL circuit of claim 9, wherein: the calibration circuit is configured to preset the control voltage based on a linear function of the temperature reading; and the linear function is defined by a slope having a numerator corresponding to an output range of the detector circuit. ### Claim 11 (depends on 9) The PLL circuit of claim 9, wherein: the calibration circuit is configured to preset the control voltage based on a linear function of the temperature reading; and the linear function is defined by a slope having a denominator corresponding to a range of ambient temperatures within which the PLL circuit operates. ### Claim 12 (depends on 9) The PLL circuit of claim 9, wherein: the calibration circuit is configured to preset the control voltage based on a linear function of the temperature reading; and the linear function includes a constant value defined by a minimum control voltage at a minimum temperature at which the PLL circuit operates. ### Claim 13 (depends on 9) The PLL circuit of claim 9, wherein: the VCO includes a varactor having a variable capacitance tunable by the control voltage for adjusting the target frequency; and the calibration circuit is configured to preset the control voltage to reduce the variable capacitance when the temperature reading is above a predetermined threshold. ### Claim 14 (depends on 9) The PLL circuit of claim 9, wherein: the VCO includes a varactor having a variable capacitance tunable by the control voltage for adjusting the target frequency; and the calibration circuit is configured to preset the control voltage to increase the variable capacitance when the temperature reading is below a predetermined threshold. ### Claim 15 A method for calibrating a phase lock loop (PLL) device, the method comprising: receiving, by a calibration circuit, a temperature reading corresponding to a junction temperature of the PLL device; determining, by the calibration circuit, an initial control voltage by applying the temperature reading to a function corresponding to a detector circuit of the PLL device and a range of ambient temperatures within which the PLL circuit operates; and generating, by the detector circuit, the initial control voltage for biasing a voltage control oscillator (VCO) of the PLL device. ### Claim 16 (depends on 15) The method of claim 15, further comprising: generating, by a temperature sensor, the temperature reading corresponding to the junction temperature of the PLL device during a calibration process. ### Claim 17 (depends on 15) The method of claim 15, further comprising: receiving, by the calibration circuit, the function having a slope defined by: a numerator corresponding to an output range of the detector circuit; and a denominator corresponding to the range of ambient temperatures within which the PLL circuit operates. ### Claim 18 (depends on 15) The method of claim 15, further comprising: receiving, by the calibration circuit, the function having a constant value defined by a minimum control voltage at a minimum temperature at which the PLL circuit operates. ### Claim 19 (depends on 15) The method of claim 15, further comprising: delivering, by the detector circuit, the initial control voltage to the VCO for reducing a variable capacitance of a varactor when the temperature reading is above a predetermined threshold. ### Claim 20 (depends on 15) The method of claim 15, further comprising: delivering, by the detector circuit, the initial control voltage to the VCO for increasing a variable capacitance of a varactor when the temperature reading is below a predetermined threshold.