# US 9,520,882 B2 · Receiver circuit of semiconductor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,882 B2 - Document ID: US9520882B2 - Status: Granted - Kind: B2 - Application number: 14/515,899 - Filed: 2014-10-16 - Published: 2016-01-07 - Granted: 2016-12-13 - Earliest claimed: 2014-07-07 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jin Ha Hwang - Web page: https://patentgrep.com/patent/US9520882B2 ## CPC - H03L 7/06: using a reference signal applied to a frequency- or phase-locked loop - H03K 3/356139: {with synchronous operation} - H03K 3/356191: {with synchronous operation} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A receiver circuit of a semiconductor apparatus may include, a latch comprising differential input terminals and differential output terminals. The receiver circuit may also include a control unit configured to selectively reset first and second intermediate nodes coupled between the differential input terminals and the differential output terminals according to previous data. ## Claims ### Claim 1 A receiver circuit of a semiconductor apparatus, comprising: a latch unit configured to change logic levels of differential output terminals according to a difference between two data inputted through differential input terminals; a reset unit configured to perform an equalization function by selectively resetting one of first and second intermediate nodes in response to control signals; and a control unit configured to generate the control signals according to a reset condition and previous input data. ### Claim 2 (depends on 1) The receiver circuit according to claim 1, wherein the reset unit is configured to reset only one of the first and second intermediate nodes in response to the control signals. ### Claim 3 (depends on 2) The receiver circuit according to claim 2, wherein a voltage level of the other intermediate node drops to a lower level than a level of a power supply terminal. ### Claim 4 (depends on 1) The receiver circuit according to claim 1, wherein the reset unit resets the differential output terminals to a level of a power supply terminal, in response to a clock signal. ### Claim 5 (depends on 1) The receiver circuit according to claim 1, wherein the control unit uses a clock signal as the reset condition. ### Claim 6 (depends on 1) The receiver circuit according to claim 1, wherein the control unit uses signals, obtained by latching outputs of the differential output terminals, as the previous input data. ### Claim 7 (depends on 1) The receiver circuit according to claim 1, wherein the control unit is configured to generate the control signals by combining a clock signal with signals obtained by latching outputs of the differential output terminals. ### Claim 8 A receiver circuit of a semiconductor apparatus, comprising: a latch unit comprising differential input terminals and differential output terminals; and a control unit configured to selectively reset one of first and second intermediate nodes according to previous data. ### Claim 9 (depends on 8) The receiver circuit according to claim 8, wherein the control unit is configured to reset only one of the first and second intermediate nodes in response to the control signals. ### Claim 10 (depends on 9) The receiver circuit according to claim 9, wherein a voltage level of the other intermediate node drops to a lower level than a level of a power supply terminal. ### Claim 11 (depends on 8) The receiver circuit according to claim 8, wherein the differential output terminals are reset to a level of a power supply terminal in response to a clock signal. ### Claim 12 (depends on 8) The receiver circuit according to claim 8, wherein the control unit is configured to determine the previous data according to signals obtained by latching outputs of the differential output terminals. ### Claim 13 (depends on 12) The receiver circuit according to claim 12, wherein the control unit is configured to selectively reset the one of the first and second intermediate nodes in response to results obtained by combining a clock signal with the signals obtained by latching the outputs of the differential output terminals. ### Claim 14 A receiver circuit of a semiconductor apparatus, comprising: a latch unit configured to change logic levels of differential output terminals according to a difference between a first data and a second data inputted through differential input terminals; a feedback signal generation unit configured to output signals obtained by latching outputs of the differential output terminals as differential feedback signals; a reset unit configured to perform an equalization function by selectively resetting one of first and second intermediate nodes in response to control signals; and a control unit configured to generate the control signals in response to the differential feedback signals and a clock signal. ### Claim 15 (depends on 14) The receiver circuit according to claim 14, wherein the reset unit is configured to reset only one of the first and second intermediate nodes in response to the control signals. ### Claim 16 (depends on 15) The receiver circuit according to claim 15, wherein a voltage level of the other intermediate node drops to a lower level than a level of a power supply terminal. ### Claim 17 (depends on 14) The receiver circuit according to claim 14, wherein the reset unit is configured to reset the differential output terminals to a level of a power supply terminal, in response to the clock signal. ### Claim 18 (depends on 1) The receiver circuit according to claim 1, wherein the first intermediate node is coupled between one of the differential input terminals and one of the differential output terminals, and wherein the second intermediate node is coupled between one of the differential input terminals different from what the first intermediate node is coupled with and one of the differential output terminals different from what the first intermediate node is coupled with. ### Claim 19 (depends on 8) The receiver circuit according to claim 8, wherein the first intermediate node is coupled between one of the differential input terminals and one of the differential output terminals, and wherein the second intermediate node is coupled between one of the differential input terminals different from what the first intermediate node is coupled with and one of the differential output terminals different from what the first intermediate node is coupled with. ### Claim 20 (depends on 14) The receiver circuit according to claim 14, wherein the first intermediate node is coupled between one of the differential input terminals and one of the differential output terminals, and wherein the second intermediate node is coupled between one of the differential input terminals different from what the first intermediate node is coupled with and one of the differential output terminals different from what the first intermediate node is coupled with.