# US 9,520,880 B2 · Configurable analog front ends for circuits with substantially gate enclosed inner electrode MOSFET switch

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- Number: US 9,520,880 B2
- Document ID: US9520880B2
- Status: Granted
- Kind: B2
- Application number: 14/170,052
- Filed: 2014-01-31
- Published: 2015-08-06
- Granted: 2016-12-13
- Earliest claimed: 2014-01-31
- Assignees: Texas Instruments Deutschland GmbH
- Applicants: Texas Instruments Deutschland GmbH
- Inventors: Bjoern Oliver Eversmann; Ralf Brederlow
- Web page: https://patentgrep.com/patent/US9520880B2

## CPC

- H03K 19/09407: {of the same canal type}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus.

## Claims

### Claim 1

A configurable integrated circuit (IC), comprising:
a substrate having a semiconductor surface that said IC is formed within and thereon, said IC including:
a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO);
an analog switch having at least a first Substantially Gate Enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain,
wherein said drain or said source is a Substantially Gate Enclosed (SGE) inner electrode relative to said gate stack and another of said source and said drain is outside said gate stack, and
an analog bus,
wherein said inner electrode of said first SGEFET is directly coupled to said analog bus, and
a switch control that provides control signals to at least said gate of said first SGEFET for controlling a connectivity between said circuit module or said IO and said analog bus.

### Claim 2 (depends on 1)

The configurable IC of claim 1, wherein said first SGEFET is a Ring-FET.

### Claim 3 (depends on 1)

The configurable IC of claim 1, wherein said analog switch consists of a single transistor.

### Claim 4 (depends on 1)

The configurable IC of claim 1, wherein said analog switch further comprises a second SGEFET configured with said first SGEFET to provide a first transmission gate (TG).

### Claim 5 (depends on 4)

The configurable IC of claim 4, wherein said analog switch further comprises a third SGEFET and a fourth SGEFET configured together to provide a second TG, said first TG and said second TG in a cascaded TG arrangement having an intermediate node between said first TG and said second TG.

### Claim 6 (depends on 5)

The configurable IC of claim 5, wherein said switch control is coupled to both said gate and a body of said first SGEFET and a gate and a body of said second SGEFET in said first TG, to a gate and a body of said third SGEFET and to a gate and a body of said fourth SGEFET in said second TG.

### Claim 7 (depends on 5)

The configurable IC of claim 5, further comprising a buffer having an input coupled to a node including said inner electrode of said first SGEFET in said first TG through said analog bus and an output coupled to said switch control.

### Claim 8 (depends on 5)

The configurable IC of claim 5, wherein said analog switch comprises a cascaded multiplexer circuit.

### Claim 9 (depends on 1)

The configurable IC of claim 1, wherein said circuit module consists of at least one selected from the group consisting of an operational amplifier, an instrumentation amplifier, a transconductance amplifier, a power amplifier (PA), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an integrator, a filter, a mixer, a comparator, a modulator, and an oscillator.

### Claim 10 (depends on 1)

The configurable IC of claim 1, wherein said configurable IC comprises a microcontroller unit (MCU), said MCU including:
said switch control, a program memory, digital I/O interface, and a central processing unit (CPU) each coupled to an address bus and to a data bus,
wherein said analog switch comprises at least one switch matrix including said first SGEFET and at least a second SGEFET,
wherein said at least one circuit module or input/output (IO) comprises a plurality of said circuit modules, and
wherein said switch control is coupled to said analog bus by said switch matrix.

### Claim 11 (depends on 10)

The configurable IC of claim 10, wherein said switch matrix consists of a single switch matrix.

### Claim 12 (depends on 10)

The configurable IC of claim 10, wherein said switch matrix includes a plurality of said switch matrices, wherein at least one of said plurality of said switch matrices is inside one of said plurality of said circuit modules or said IO's.

### Claim 13

A configurable integrated circuit (IC), comprising:
a substrate having a semiconductor surface that said IC is formed within and thereon, said IC including:
a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO);
an analog switch having at least a first Ring-FET having a gate stack including a gate on a gate dielectric, a source, and a drain,
wherein said drain or said source is an enclosed inner electrode relative to said gate stack and another of said source and said drain is outside said gate stack, and
an analog bus,
wherein said inner electrode of said first Ring-FET is directly coupled to said analog bus, and
a switch control that provides control signals to at least said gate of said first Ring-FET for controlling a connectivity between said circuit module or said IO and said analog bus.

### Claim 14 (depends on 13)

The configurable IC of claim 13, wherein said analog switch further comprises a second Ring-FET configured with said first Ring-FET to provide a first transmission gate (TG).

### Claim 15 (depends on 14)

The configurable IC of claim 14, wherein said analog switch further comprises a third Ring-FET and a fourth Ring-FET configured together to provide a second TG, said first TG and said second TG in a cascaded TG arrangement having an intermediate node between said first TG and said second TG.

### Claim 16 (depends on 15)

The configurable IC of claim 15, wherein said switch control is coupled to said gate and a body of said first Ring-FET and to a gate and a body of said second Ring-FET in said first TG, and to a gate and a body of said third Ring-FET and to a gate and a body of said fourth Ring-FET in said second TG.

### Claim 17 (depends on 15)

The configurable IC of claim 15, further comprising a buffer having an input coupled to a node including said inner electrode of said first Ring-FET in said first TG through said analog bus and an output coupled to said switch control.

### Claim 18 (depends on 15)

The configurable IC of claim 15, wherein said analog switch comprises a cascaded multiplexer circuit.