# US 9,520,879 B2 · Adaptive blanking timer for short circuit detection

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- Number: US 9,520,879 B2
- Document ID: US9520879B2
- Status: Granted
- Kind: B2
- Application number: 14/742,540
- Filed: 2015-06-17
- Published: 2015-12-24
- Granted: 2016-12-13
- Earliest claimed: 2014-06-18
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Ruochen Zhang; Xiaofan Qiu; Jingwei Xu; Qingjie Ma
- Web page: https://patentgrep.com/patent/US9520879B2

## CPC

- H03K 17/165: {by feedback from the output circuit to the control circuit}
- H03K 17/0822: {in field-effect transistor switches}
- H03K 17/284: in field effect transistor switches
- H03K 19/017509: {Interface arrangements}
- H03K 2217/0027: Measuring means of, e.g. currents through or voltages across the switch
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low. The adaptive masking circuitry detects a Miller plateau in the gate voltage of the external NMOS transistor. The adaptive masking circuitry stops masking the output of the comparator after the end of the Miller plateau.

## Claims

### Claim 1

A gate driver integrated circuit for driving an external n-type MOSFET (NMOS) transistor having a gate, a drain and a source, the drain being coupled through a load to a power supply, the gate driver integrated circuit comprising:
a gate driver output configured to drive the gate of the external NMOS transistor;
a first comparator operable to receive the drain voltage of the external NMOS transistor and compare it to a reference voltage representative of a short circuit condition between the drain and the power supply, the first comparator being configured to output a first value if the drain voltage is greater than the reference voltage and to output a second value if the drain voltage is less than or equal to the reference voltage;
control circuitry configured to receive the output of the first comparator and to pull the voltage of the gate driver output low if the comparator output is of the first value;
adaptive masking circuitry operable, upon an application of an “on” signal to the gate driver output, to mask the output of the first comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low, the adaptive masking circuitry being operable to detect a Miller plateau in the gate voltage of the external NMOS transistor, wherein the adaptive masking circuitry is operable to stop masking the output of the first comparator after the end of said Miller plateau.

### Claim 2 (depends on 1)

The gate driver integrated circuit of claim 1, wherein if the adaptive masking circuitry fails to detect a Miller plateau in the gate voltage of the external NMOS transistor, the adaptive masking circuitry is operable to stop masking the comparator output after the gate of the external NMOS transistor becomes fully charged.

### Claim 3 (depends on 1)

The gate driver integrated circuit of claim 1, wherein said masking of the output of the first comparator by the adaptive masking circuitry comprises preventing said first value of the comparator output from being provided to the control circuitry.

### Claim 4 (depends on 1)

The gate driver integrated circuit of claim 1, further comprising a gate driver MOSFET transistor configured to receive an input signal at its gate and to provide a gate driver signal to the gate driver output of the gate driver integrated circuit.

### Claim 5 (depends on 4)

The gate driver integrated circuit of claim 4, wherein the adaptive masking circuitry comprises a second comparator operable to compare the drain voltage and source voltage of the gate driver MOSFET, wherein the second comparator is operable to output a first value if the difference between the drain voltage and source voltage is less than a predetermined threshold value, and to output a second value if the difference between the drain voltage and source voltage is greater than the predetermined threshold value, wherein if the output of the second comparator comprises said second value, the adaptive masking circuitry is operable to prevent the first value of the output of the first comparator from being provided to the control circuitry.

### Claim 6 (depends on 5)

The gate driver integrated circuit of claim 5, wherein said first output value of the first comparator is a logical “1,” said second output value of the first comparator is a logical “0,” said first output value of the second comparator is a logical “1,” and said second output value of the second comparator is a logical “0,” and wherein the adaptive masking circuitry further comprises an AND gate having a first input that receives the output of the first comparator, a second input that receives the output of the second comparator, and an output that is provided to the control circuitry, wherein the control circuitry is operable to pull the voltage of the gate driver output low if the output of the AND gate is a logical “1”.