# US 9,520,877 B2 · Apparatus and method for detecting or repairing minimum delay errors

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- Number: US 9,520,877 B2
- Document ID: US9520877B2
- Status: Granted
- Kind: B2
- Application number: 14/572,031
- Filed: 2014-12-16
- Published: 2016-06-16
- Granted: 2016-12-13
- Earliest claimed: 2014-12-16
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Pascal A. Meinerzhagen; Sandip Kundu; James W. Tschanz; Vivek K. De
- Web page: https://patentgrep.com/patent/US9520877B2

## CPC

- H03K 19/00323: {Delay compensation}
- H03K 5/26: the characteristic being duration, interval, position, frequency, or sequence
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.

## Claims

### Claim 1

An apparatus, comprising:
a clock circuit to receive a first clock signal with a first frequency and to output a second clock signal, wherein the clock circuit is to output the second clock signal with the first frequency in a normal operation mode, and wherein the clock circuit is to output the second clock signal with a second frequency in a minimum-delay debug mode, wherein the second frequency in the minimum-delay debug mode is lower than the first frequency in the normal operation mode; and
a minimum-delay error detector (MDED), coupled to the clock circuit, to receive a data signal from a data path, to receive the second clock signal, and to detect a minimum-delay error (MDE) in the data path based on the received data signal and the second clock signal in the minimum-delay debug mode; and
a clocked storage circuit, coupled to the clock circuit, to receive the data signal and the second clock signal with the first frequency during the normal operation mode, and to receive the data signal and the second clock signal with the second frequency during the minimum-delay debug mode.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the MDED comprises a dual-edge triggered flip-flop.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the dual-edge triggered flip-flop comprises a transparent-on-high latch, a transparent-on-low latch, and an output multiplexer, the transparent-on-high latch and the transparent-on-low latch to receive the data signal at respective clock terminals and to receive the second clock signal at respective data terminals.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the output multiplexer is to receive the data signal, and is to select an output from a non-transparent latch selected from the transparent-on-high latch and the transparent-on-low latch.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the MDED further comprises an inverter, coupled to the multiplexer, to output an error signal for the MDE in response to a predetermined clock phase sampled by the dual-edge triggered flip-flop.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the MDED comprises dynamic Domino logic and a static latch coupled to the Domino logic.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the Domino logic comprises a plurality of first-level stages and a second-level stage coupled to the plurality of first-level stages; wherein the plurality of first-level stages and the second-level stage are pre-charged or pre-discharged during a first phase of the second clock signal; and
wherein the second-level stage is to generate an MDE flag when the data signal changes state during a second phase of the second clock signal.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the static latch is to remain set in response to the detected MDE until a system reset.

### Claim 9 (depends on 1)

The apparatus of claim 1, further comprising:
a clock buffer, coupled to the MDED, to adjust the second clock signal to repair the MDE in response to the detected MDE.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the clock buffer is a post-silicon tunable (PST) clock buffer; and wherein the PST clock buffer is to shorten a delay to the second clock signal when the minimum-delay error is detected.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the clock buffer is a regional clock buffer (RCB); wherein the RCB is coupled to the MDED and at least another MDED in a clock domain clocked by the RCB; and
wherein the RCB is to shorten a delay to the second clock signal based on the minimum-delay error detected by the MDED or another minimum-delay error detected by at least another MDED.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the second frequency of the second clock signal is lower than or equal to a half of the first frequency.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the MDED is to detect the MDE in the data path based on a data transition at a predetermined clock phase of the second clock signal.

### Claim 14

An apparatus comprising:
a clock circuit to receive a first clock signal with a first frequency and to output a second clock signal, wherein the clock circuit is to output the second clock signal with the first frequency in a normal operation mode, and wherein the clock circuit is to output the second clock signal with a second frequency in a minimum-delay debug mode, wherein the second frequency in the minimum-delay debug mode is lower than the first frequency in the normal operation mode; and
a minimum-delay error detector (MDED), coupled to the clock circuit, to receive a data signal from a data path, to receive the second clock signal, and to detect a minimum-delay error (MDE) in the data path based on the received data signal and the second clock signal in the minimum-delay debug mode, wherein the MDED comprises a dual-edge triggered flip-flop, and wherein the dual-edge triggered flip-flop comprises a transparent-on-high latch, a transparent-on-low latch, and an output multiplexer, the transparent-on-high latch and the transparent-on-low latch to receive the data signal at respective clock terminals and to receive the second clock signal at respective data terminals.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the output multiplexer is to receive the data signal, and is to select an output from a non-transparent latch selected from the transparent-on-high latch and the transparent-on-low latch.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the MDED further comprises an inverter, coupled to the multiplexer, to output an error signal for the MDE in response to a predetermined clock phase sampled by the dual-edge triggered flip-flop.