# US 9,520,876 B1 · Power gating and clock gating in wiring levels > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,876 B1 - Document ID: US9520876B1 - Status: Granted - Kind: B1 - Application number: 15/045,753 - Filed: 2016-02-17 - Granted: 2016-12-13 - Earliest claimed: 2016-02-17 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Nathaniel R. Chadwick; Tassbieh Hassan; Kirk D. Peterson; John E. Sheets, II; Christine E. Whiteside - Web page: https://patentgrep.com/patent/US9520876B1 ## CPC - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices} - G06F 13/4081: {Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004)} - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/36: Circuit design at the analogue level - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/396: Clock trees - H03K 19/018585: {programmable} - H03K 19/096: Synchronous circuits, i.e. using clock signals {(H03K19/01728, H03K19/01855 take precedence)} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 70/095: {of vias therein} - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 90/00: Package configurations - G06F 2117/04: Clock gating - G06F 2119/06: Power analysis or power optimisation - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor comprising a front end of line portion including a logical processing unit (LPU) and a second LPU. The first LPU configured to perform a first operation and the second LPU configured to perform a second operation following the first operation. A back end of line portion including a plurality of wiring levels, and further including a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels. The power gate and clock gate are further electrically connected to the first LPU by an enable wire. The power gate and clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU. A signal wire is electrically connected to the first LPU and to the latch. ## Claims ### Claim 1 A semiconductor comprising: a front end of line portion that includes a first logical processing unit (LPU) and a second LPU, the first LPU designed to perform a first operation and the second LPU designed to perform a second operation following the first operation; a back end of line (BEOL) portion that includes a plurality of wiring levels, and further includes a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels, the power gate and the clock gate are further electrically connected to the first LPU by an enable wire, the power gate and the clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU; and a signal wire is electrically connected to the first LPU, and is also electrically connected to the latch. ### Claim 2 (depends on 1) The semiconductor of claim 1, wherein the power gate, clock gate, power grid, and clock net are integrated into a same wiring level of the one or more wiring levels. ### Claim 3 (depends on 1) The semiconductor of claim 1, wherein the latch is configured to activate the second LPU in response to receiving an electrical signal from both the enable wire and the signal wire. ### Claim 4 (depends on 1) The semiconductor of claim 1, wherein the power gate is integrated into an electrical via of the one or more wiring levels. ### Claim 5 (depends on 1) The semiconductor of claim 1, wherein the clock gate is integrated into an electrical via of the one or more wiring levels. ### Claim 6 (depends on 1) The semiconductor of claim 1, wherein the power grid is integrated into an electrical via of the one or more wiring levels. ### Claim 7 (depends on 1) The semiconductor of claim 1, wherein the clock net is integrated into an electrical via of the one or more wiring levels. ### Claim 8 (depends on 1) The semiconductor of claim 1, wherein the power gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the clock net, that activates the power grid. ### Claim 9 (depends on 1) The semiconductor of claim 1, wherein the clock gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the power grid, that activates the clock net. ### Claim 10 (depends on 1) The semiconductor of claim 1, wherein the one or more wiring levels that include the power gate and the clock gate are located vertically above the power grid and the clock net. ### Claim 11 (depends on 10) The semiconductor of claim 10, wherein the power gate and the clock gate are integrated into a same wiring level of the one or more wiring levels. ### Claim 12 (depends on 10) The semiconductor of claim 10, wherein the power gate and the clock gate are integrated into different wiring levels of the one or more wiring levels. ### Claim 13 A semiconductor system comprising: a first logical processing unit (LPU) integrated in a front end of line portion transmitting an electrical signal, in response to a first operation being performed be the first LPU, via an enable wire to a power gate and a clock gate, the power gate and the clock gate are integrated into one or more wiring levels of a plurality of wiring levels of a back end of line (BEOL) portion; the power gate and the clock gate activating a power grid and a clock net, respectively; the enable wire transmitting an electrical signal to a latch of a second LPU once the power grid and the clock net are activated; a signal wire transmitting an electrical signal, in response to the first operation being performed, to the latch; and the second LPU being activated to perform a second operation in response to the latch receiving the electrical signal from the signal wire and the enable wire. ### Claim 14 (depends on 13) The semiconductor system of claim 13, wherein the latch is configured to activate the second LPU in response to receiving an electrical signal from both the enable wire and the signal wire. ### Claim 15 (depends on 13) The semiconductor system of claim 13, wherein the power gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the clock net, that activates the power grid. ### Claim 16 (depends on 13) The semiconductor system of claim 13, wherein the clock gate is a thin film field effect transistor that is configured to transmit an electrical signal, in response to receiving an electrical signal exiting the power grid, that activates the clock net. ### Claim 17 (depends on 13) The semiconductor system of claim 13, wherein the one or more wiring levels that include the power gate and the clock gate are located vertically above the power grid and the clock net. ### Claim 18 (depends on 17) The semiconductor system of claim 17, wherein the power gate and the clock gate are integrated into a same wiring level of the one or more wiring levels. ### Claim 19 (depends on 17) The semiconductor system of claim 17, wherein the power gate and the clock gate are integrated into different wiring levels of the one or more wiring levels.