# US 9,520,865 B2 · Delay circuits and related systems and methods

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- Number: US 9,520,865 B2
- Document ID: US9520865B2
- Status: Granted
- Kind: B2
- Application number: 14/477,367
- Filed: 2014-09-04
- Published: 2016-03-10
- Granted: 2016-12-13
- Earliest claimed: 2014-09-04
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Lior Amarilio; Alexander Golubitski; Haim Hagay Haller; Felix Kolmakov; Gilad Sthoeger
- Web page: https://patentgrep.com/patent/US9520865B2

## CPC

- H03K 5/133: using a chain of active delay devices
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 13/4068: {Electrical coupling}
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers
- H03K 5/13: Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K 2005/0015: {Layout of the delay element}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

## Claims

### Claim 1

A delay circuit for delaying an output enable signal, comprising:
a first shift register chain comprising:
a first chain input configured to receive an output enable in signal, wherein the output enable in signal is based on a slow clock signal;
a first chain clock input configured to receive a fast clock signal; and
a first chain output configured to provide a first strobe signal;
a second shift register chain comprising:
a second chain input configured to receive the output enable in signal;
a second chain clock input configured to receive the fast clock signal; and
a second chain output configured to provide a second strobe signal, wherein each transition of the second strobe signal is opposite of a corresponding transition of the first strobe signal; and
a delayed output configured to provide an output enable out signal based on the first strobe signal, the second strobe signal, and the output enable in signal.

### Claim 2 (depends on 1)

The delay circuit of claim 1, further comprising a flip-flop comprising:
a flip-flop input configured to receive a data signal;
a flip-flop clock input configured to receive the slow clock signal; and
a flip-flop output configured to provide the output enable in signal.

### Claim 3 (depends on 1)

The delay circuit of claim 1, further comprising a fast clock configured to provide the fast clock signal.

### Claim 4 (depends on 3)

The delay circuit of claim 3, wherein the fast clock comprises a ring oscillator.

### Claim 5 (depends on 1)

The delay circuit of claim 1, further comprising an OR-based logic gate comprising:
a first OR-based input configured to receive the first strobe signal;
a second OR-based input configured to receive the second strobe signal; and
an OR-based output.

### Claim 6 (depends on 5)

The delay circuit of claim 5, further comprising an AND-based logic gate comprising:
a first AND-based input configured to receive the output enable in signal;
a second AND-based input coupled to the OR-based output; and
the delayed output.

### Claim 7 (depends on 1)

The delay circuit of claim 1, wherein:
the first shift register chain comprises an even number of first shift elements; and
the second shift register chain comprises an even number of second shift elements.

### Claim 8 (depends on 1)

The delay circuit of claim 1, further comprising a frequency compensation circuit configured to:
receive the fast clock signal;
receive the slow clock signal; and
compensate the output enable out signal based on a delay variance between the slow clock signal and the fast clock signal.

### Claim 9 (depends on 8)

The delay circuit of claim 8, wherein the frequency compensation circuit comprises:
a counter circuit configured to count a number of fast clock signal transitions that occur during a cycle of the slow clock signal; and
the frequency compensation circuit further configured to determine the delay variance between the slow clock signal and the fast clock signal based on the number of counted fast clock signal transitions.

### Claim 10 (depends on 8)

The delay circuit of claim 8, wherein:
the frequency compensation circuit is further configured to provide a selection signal based on the delay variance; and
the delay circuit further comprises:
a multiplexer, wherein data inputs of the multiplexer are coupled to individual elements within the first shift register chain and individual elements within the second shift register chain; and
the multiplexer is configured to:
provide the first strobe signal based on the selection signal received from the frequency compensation circuit; and
provide the second strobe signal based on the selection signal received from the frequency compensation circuit.

### Claim 11 (depends on 1)

The delay circuit of claim 1, further comprising a power reduction circuit configured to pause the fast clock signal when the output enable in signal and the output enable out signal are logically equal.

### Claim 12 (depends on 4)

The delay circuit of claim 4, further comprising:
a power reduction circuit configured to pause the fast clock signal when the output enable in signal and the output enable out signal are logically equal; and
the power reduction circuit comprises an XOR-based logic gate configured to:
receive the output enable in signal and the output enable out signal; and
provide a power reduction signal.

### Claim 13 (depends on 12)

The delay circuit of claim 12, wherein the ring oscillator comprises:
a plurality of serially coupled inverters; and
an AND-based logic gate configured to:
receive an inverter signal from a final inverter from among the plurality of serially coupled inverters;
receive the power reduction signal; and
provide the fast clock signal.

### Claim 14 (depends on 1)

The delay circuit of claim 1 integrated into an integrated circuit (IC).

### Claim 15 (depends on 1)

The delay circuit of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

### Claim 16

A method for delaying an output enable signal, comprising:
receiving a fast clock signal;
receiving a slow clock signal;
receiving an output enable in signal, wherein the output enable in signal is based on the slow clock signal;
generating a first strobe signal based on the output enable in signal and the fast clock signal;
generating a second strobe signal based on the output enable in signal and the fast clock signal, wherein each transition of the second strobe signal is opposite of each corresponding transition of the first strobe signal; and
providing an output enable out signal based on the first strobe signal, the second strobe signal, and the output enable in signal.

### Claim 17 (depends on 16)

The method of claim 16, further comprising compensating the output enable out signal based on a delay variance between the slow clock signal and the fast clock signal.

### Claim 18 (depends on 17)

The method of claim 17, wherein compensating the output enable out signal comprises:
counting a number of fast clock signal transitions that occur during a cycle of the slow clock signal; and
determining the delay variance between the slow clock signal and the fast clock signal based on the number of counted fast clock signal transitions.

### Claim 19 (depends on 16)

The method of claim 16, further comprising pausing the fast clock signal when the output enable in signal is logically equal to the output enable out signal.

### Claim 20

A delay circuit for delaying an output enable, comprising:
a first shift register chain configured to generate a first strobe signal;
a second shift register chain configured to generate a second strobe signal, wherein each transition of the second strobe signal is opposite of each corresponding transition of the first strobe signal; and
a delayed output configured to provide an output enable out signal based on the first strobe signal, the second strobe signal, and an input signal.

### Claim 21 (depends on 20)

The delay circuit of claim 20, further comprising an OR-based logic gate comprising:
a first OR-based input configured to receive the first strobe signal;
a second OR-based input configured to receive the second strobe signal; and
an OR-based output.

### Claim 22 (depends on 21)

The delay circuit of claim 21, further comprising an AND-based logic gate comprising:
a first AND-based input configured to receive the input signal;
a second AND-based input coupled to the OR-based output; and
the delayed output.

### Claim 23 (depends on 20)

The delay circuit of claim 20, further comprising a frequency compensation circuit configured to:
receive a fast clock signal;
receive a slow clock signal; and
compensate the output enable out signal based on a delay variance between the slow clock signal and the fast clock signal.

### Claim 24 (depends on 20)

The delay circuit of claim 20, further comprising a power reduction circuit configured to pause a fast clock signal when the input signal and the output enable out signal are logically equal.

### Claim 25

A system comprising:
a communications bus compliant with SoundWire™ protocol, the communications bus comprising:
a data wire; and
a clock wire;
a master device coupled to one or more slave devices via the communications bus; and
each of the one or more slave devices comprising a delay circuit, wherein each delay circuit among a plurality of delay circuits comprises:
a first shift register chain comprising:
a first chain input configured to receive an output enable in signal, wherein the output enable in signal is based on a slow clock signal provided on the clock wire;
a first chain clock input configured to receive a fast clock signal; and
a first chain output configured to provide a first strobe signal; and
a second shift register chain comprising:
a second chain input configured to receive the output enable in signal;
a second chain clock input configured to receive the fast clock signal; and
a second chain output configured to provide a second strobe signal, wherein each transition of the second strobe signal is opposite of each corresponding transition of the first strobe signal; and
a delayed output configured to provide an output enable out signal based on the first strobe signal, the second strobe signal, and the output enable in signal.