# US 9,520,863 B2 · Dual-port negative level sensitive preset data retention latch

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,520,863 B2
- Document ID: US9520863B2
- Status: Granted
- Kind: B2
- Application number: 14/447,911
- Filed: 2014-07-31
- Published: 2015-02-26
- Granted: 2016-12-13
- Earliest claimed: 2013-08-26
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Steven C. Bartling; Sudhanshu Khanna
- Web page: https://patentgrep.com/patent/US9520863B2

## CPC

- H03K 3/356008: {ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

## Claims

### Claim 1

A dual-port negative level sensitive preset data retention latch comprising:
a clocked inverter configured to receive a first data bit, a first clock signal, a second clock signal, a preset control signal and a first retention mode control signal wherein the first clock signal, the second clock signal, the preset control signal and the first retention mode control signal determine whether a data output from the clocked inverter is the binary compliment of the first data bit or an indeterminate value;
a dual-port latch configured to receive the data output of the clocked inverter, a second data bit, the first clock signal, the second clock signal, the first retention mode control signal, a second retention mode control signal, the preset control signal, a first latch control signal and a second latch control signal wherein the first clock signal, the second clock signal, the first retention mode control signal, the second retention mode control signal, the preset control signal, the first latch control signal and a second latch control signal determine whether the data output of the clocked inverter or the second data bit is latched in the dual-port latch;
wherein the output of the clocked inverter is received by the dual-port latch when the first clock signal changes from a high logical signal to a low logical signal; and
wherein the dual-port latch is latched when the first clock signal changes from a low logical signal to a high logical signal.

### Claim 2 (depends on 1)

The dual-port negative level sensitive preset data retention latch of claim 1, further comprising a first inverter wherein the first inverter receives the data output of the clocked inverter and the first inverter outputs the binary compliment of the data output of the clocked inverter.

### Claim 3 (depends on 2)

The dual-port negative level sensitive preset data retention latch of claim 2 wherein the clocked inverter and the first inverter receive power from a first power supply; wherein the dual-port latch receives power form a second power supply.

### Claim 4 (depends on 3)

The dual-port negative level sensitive latch of claim 3 wherein the first power supply is turned off and the second power supply is turned on during operation of a retention mode; wherein power is only supplied to the dual-port latch and a logic circuit.

### Claim 5 (depends on 1)

The dual-port negative level sensitive preset data retention latch of claim 1, further comprising a buffer wherein the buffer receives the data output of the clocked inverter and the buffer outputs the same logical value of the data output of the clocked inverter.

### Claim 6 (depends on 1)

The dual-port negative level sensitive preset data retention latch of claim 1 wherein control signals the first latch control signal, the second latch control signal, the preset control signal, the first retention mode control signal and the second retention mode control signal are controlled external to the dual-port negative level sensitive preset data retention latch to prevent data contention between the data output from the clocked inverter and the second data bit.

### Claim 7 (depends on 1)

The dual-port negative level sensitive preset data retention latch of claim 1 wherein the dual-port latch comprises:
a first tri-state inverter, the first tri-state inverter having a data input, two control inputs and a data output wherein the data input is electrically connected to the data output of the clocked inverter, the first control input is electrically connected to the first latch control signal, and the second control input is connected to the second latch control signal;
a second tri-state inverter, the second tri-state inverter having a data input, two control inputs and a data output wherein the data input is electrically connected to the second data bit, the first control input is electrically connected to the first latch control signal, and the second control input is connected to the second latch control signal and the outputs of the first and second tri-state inverter are electrically connected to each other;
a clocked inverter, the clocked inverter having a data input, five control inputs and a data output wherein the data input is electrically connected to the data output of the first and second tri-state inverters, a first control input is electrically connected to the first clock signal, a second control input is connected to the first clock signal, a third control input is electrically connected to the first retention mode control signal, a fourth control input to the second retention mode control signal, a fifth control input is connected to the preset control signal and the output of the clocked inverter is electrically connected to the input of the first tri-state inverter.