# US 9,520,854 B2 · Tunable capacitor integrated on one semiconductor die or on one module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,854 B2 - Document ID: US9520854B2 - Status: Granted - Kind: B2 - Application number: 14/013,235 - Filed: 2013-08-29 - Published: 2014-01-02 - Granted: 2016-12-13 - Earliest claimed: 2012-04-03 - Assignees: HiDeep Inc. - Applicants: HiDeep Inc - Inventors: Bonkee Kim; Youngho Cho; Donggu Im; Bumkyum Kim - Web page: https://patentgrep.com/patent/US9520854B2 ## CPC - H03H 7/38: Impedance-matching networks - H03H 11/28: Impedance matching networks - H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)} - H10W 44/234: {Arrangements for impedance matching} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed is a tunable capacitor. The tunable capacitor according to a first embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L. The tunable capacitor according to a second embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L, and wherein the tunable capacitor is integrated on one semiconductor die or on one module. ## Claims ### Claim 1 A tunable capacitor comprising: a first capacitor; a switching transistor which switches on/off a connection of the first capacitor between a first terminal and a second terminal; and a converter configured to convert a signal applied to a gate terminal G of the switching transistor and apply the converted signal to a drain terminal D and a source terminal S of the switching transistor, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L. ### Claim 2 (depends on 1) The tunable capacitor of claim 1, wherein when the switching transistor is in an on-state, a high signal H is applied to the gate terminal G, and a low signal L is applied to a body terminal B, the drain terminal D and the source terminal S, and wherein when the switching transistor is in an off-state, the low signal L is applied to the gate terminal G and the body terminal B, and the high signal H is applied to the drain terminal D and the source terminal S. ### Claim 3 (depends on 1) The tunable capacitor of claim 1, wherein the switching transistor is a stacked transistor formed by connecting in series a plurality of transistors. ### Claim 4 (depends on 1) The tunable capacitor of claim 1, wherein the gate terminal G and a body terminal B of the switching transistor are connected in series to a resistance respectively. ### Claim 5 (depends on 1) The tunable capacitor of claim 1, wherein the first capacitor is formed by connecting in series or in parallel a plurality of capacitors. ### Claim 6 (depends on 1) A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 1, wherein the plurality of the tunable capacitors are connected in parallel to each other. ### Claim 7 (depends on 1) A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 1, wherein the plurality of the tunable capacitors are connected in parallel to each other. ### Claim 8 (depends on 6) The tunable capacitor array of claim 6, wherein an equivalent capacitance of the plurality of the tunable capacitors is 2m-1×C1 (here, m is a natural number less than or equal to n), wherein channel width-to-length ratios W/L of the switching transistors of the plurality of the tunable capacitors are 2m-1×W1 (here, m is a natural number less than or equal to n) respectively, and wherein the n is a number of the tunable capacitors, wherein the C1 is an equivalent capacitance of a particular tunable capacitor, and wherein the W1 is a channel width-to-length ratio W/L of the switching transistor. ### Claim 9 (depends on 6) The tunable capacitor array of claim 6, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors. ### Claim 10 (depends on 8) The tunable capacitor array of claim 8, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors. ### Claim 11 (depends on 6) The tunable capacitor array of claim 6, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor. ### Claim 12 (depends on 8) The tunable capacitor array of claim 8, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor. ### Claim 13 A tunable capacitor comprising: a first capacitor; a switching transistor which switches on/off a connection of the first capacitor between a first terminal and a second terminal; and a converter configured to convert a signal applied to a gate terminal G of the switching transistor and apply the converted signal to a drain terminal D and a source terminal S of the switching transistor, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L, and wherein the tunable capacitor is integrated on one semiconductor die or on one module. ### Claim 14 (depends on 13) The tunable capacitor of claim 13, wherein when the switching transistor is in an on-state, a high signal H is applied to the gate terminal G, and a low signal L is applied to a body terminal B, the drain terminal D and the source terminal S, and wherein when the switching transistor is in an off-state, the low signal L is applied to the gate terminal G and the body terminal B, and the high signal H is applied to the drain terminal D and the source terminal S. ### Claim 15 (depends on 13) The tunable capacitor of claim 13, wherein the switching transistor is a stacked transistor formed by connecting in series a plurality of transistors. ### Claim 16 (depends on 13) The tunable capacitor of claim 13, wherein the gate terminal G and a body terminal B of the switching transistor are connected in series to a resistance respectively. ### Claim 17 (depends on 13) The tunable capacitor of claim 13, wherein the first capacitor is formed by connecting in series or in parallel a plurality of capacitors. ### Claim 18 (depends on 13) A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 13, wherein the plurality of the tunable capacitors are connected in parallel to each other. ### Claim 19 (depends on 13) A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 13, wherein the plurality of the tunable capacitors are connected in parallel to each other. ### Claim 20 (depends on 18) The tunable capacitor array of claim 18, wherein an equivalent capacitance of the plurality of the tunable capacitors is 2m-1×C1 (here, m is a natural number less than or equal to n), wherein channel width-to-length ratios W/L of the switching transistors of the plurality of the tunable capacitors are 2m-1×W1 (here, m is a natural number less than or equal to n) respectively, and wherein the n is a number of the tunable capacitors, wherein the C1 is an equivalent capacitance of a particular tunable capacitor, and wherein the W1 is a channel width-to-length ratio W/L of the switching transistor. ### Claim 21 (depends on 18) The tunable capacitor array of claim 18, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors. ### Claim 22 (depends on 20) The tunable capacitor array of claim 20, further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors. ### Claim 23 (depends on 18) The tunable capacitor array of claim 18, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor. ### Claim 24 (depends on 20) The tunable capacitor array of claim 20, further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.