# US 9,520,846 B2 · Current-driven baseband filter with reduced adjacent channel leakage ratio (ACLR)

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- Number: US 9,520,846 B2
- Document ID: US9520846B2
- Status: Granted
- Kind: B2
- Application number: 14/711,194
- Filed: 2015-05-13
- Published: 2016-11-17
- Granted: 2016-12-13
- Earliest claimed: 2015-05-13
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Seyed Hossein Miri Lavasani; Cheng-Han Wang; Abbas Komijani; Mohammad Bagher Vahid Far
- Web page: https://patentgrep.com/patent/US9520846B2

## CPC

- H03F 3/19: with semiconductor devices only
- H03F 1/0205: {in transistor amplifiers}
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H04B 1/04: Circuits
- H04B 1/1036: {with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters (H04B1/123 takes precedence; filter circuits H03H)}
- H03F 2200/294: the amplifier being a low noise amplifier [LNA]
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2203/45306: the common gate stage implemented as dif amp eventually for cascode dif amp
- H04B 2001/1045: {Adjacent-channel interference}
- H03F: AMPLIFIERS
- H04B: TRANSMISSION

## Abstract

Certain aspects of the present disclosure provide methods and apparatus for processing an input signal. One example apparatus is a circuit that generally includes an amplifier, comprising a first transistor and a second transistor connected in cascode with the first transistor; a buffer coupled to an output of the amplifier and configured to provide feedback to the amplifier; and a current source coupled to the second transistor and incorporated into a loop of the feedback to the amplifier.

## Claims

### Claim 1

A circuit comprising:
an amplifier comprising:
a first transistor; and
a second transistor connected in cascode with the first transistor, wherein a source of the first transistor is coupled to an input of the amplifier and wherein a drain of the first transistor is coupled to a source of the second transistor;
a buffer coupled to an output of the amplifier and configured to provide feedback to the amplifier; and
a current source coupled to the second transistor and incorporated into a loop of the feedback to the amplifier.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the current source comprises a third transistor and wherein a gate of the third transistor is coupled to the loop of the feedback.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the buffer comprises a source follower having a fourth transistor, wherein a gate of the fourth transistor is coupled to the output of the amplifier, and wherein a source of the fourth transistor is coupled to the gate of the third transistor.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the amplifier further comprises a fifth transistor, wherein the input of the amplifier is coupled to a drain of the fifth transistor and to the source of the first transistor, and wherein the feedback to the amplifier is configured to drive a gate of the fifth transistor.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the first and second transistors are connected in a folded cascode architecture, wherein the first transistor comprises an n-channel metal oxide semiconductor field effect (NMOS) transistor, and wherein the second transistor comprises a p-channel metal oxide semiconductor field effect (PMOS) transistor.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the output of the amplifier comprises a drain of the second transistor.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the amplifier comprises a transimpedance amplifier.

### Claim 8 (depends on 1)

The circuit of claim 1, further comprising a first passive filter coupled with the input of the amplifier and a second passive filter coupled with an output of the buffer.

### Claim 9

A method for processing an input signal, comprising:
amplifying, via an amplifier, the input signal, wherein the amplifier comprises a first transistor connected in cascode with a second transistor, wherein a source of the first transistor is coupled to an input node of the amplifier, and wherein a drain of the first transistor is coupled to a source of the second transistor;
buffering, via a buffer, an output signal of the amplifier to generate a buffered signal; and
feeding the buffered signal back to the amplifier via a feedback loop, wherein a current source is coupled to the second transistor and incorporated into the feedback loop.

### Claim 10 (depends on 9)

The method of claim 9, wherein the current source comprises a third transistor and wherein a gate of the third transistor is coupled to the feedback loop.

### Claim 11 (depends on 10)

The method of claim 10, wherein the buffer comprises a source follower having a fourth transistor, wherein a gate of the fourth transistor is coupled to an output node of the amplifier, and wherein a source of the fourth transistor is coupled to the gate of the third transistor.

### Claim 12 (depends on 11)

The method of claim 11, wherein the amplifier further comprises a fifth transistor, wherein the input node of the amplifier is coupled to a drain of the fifth transistor and to the source of the first transistor, and wherein feeding the buffered signal back to the amplifier comprises driving a gate of the fifth transistor.

### Claim 13 (depends on 9)

The method of claim 9, wherein the first and second transistors are connected in a folded cascode architecture, wherein the first transistor comprises an n-channel metal oxide semiconductor field effect (NMOS) transistor, and wherein the second transistor comprises a p-channel metal oxide semiconductor field effect (PMOS) transistor.

### Claim 14 (depends on 9)

The method of claim 9, wherein the output signal of the amplifier is generated at a drain of the second transistor.

### Claim 15 (depends on 9)

The method of claim 9, wherein the amplifier comprises a transimpedance amplifier.

### Claim 16

An apparatus for processing an input signal, comprising:
means for amplifying the input signal, wherein the means for amplifying comprises a first transistor connected in cascode with a second transistor, wherein a source of the first transistor is coupled to an input node of the means for amplifying and wherein a drain of the first transistor is coupled to a source of the second transistor;
means for buffering an output signal of the means for amplifying to generate a buffered signal, wherein the buffered signal is provided as feedback to the means for amplifying; and
means for sourcing current coupled to the second transistor and incorporated into a loop of the feedback to the means for amplifying.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the means for sourcing current comprises a third transistor and wherein a gate of the third transistor is driven by the buffered signal.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the means for buffering comprises a source follower having a fourth transistor, wherein a gate of the fourth transistor is coupled to an output node of the means for amplifying, and wherein a source of the fourth transistor is coupled to the gate of the third transistor.