# US 9,520,836 B1 · Multi-stage amplifier with cascode stage and DC bias regulator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,836 B1 - Document ID: US9520836B1 - Status: Granted - Kind: B1 - Application number: 14/825,485 - Filed: 2015-08-13 - Granted: 2016-12-13 - Earliest claimed: 2015-08-13 - Assignees: Raytheon Company - Applicants: Raytheon Company - Inventors: Valery S. Kaper - Web page: https://patentgrep.com/patent/US9520836B1 ## CPC - H03F 1/086: {with FET's} - H03F 1/223: {with MOSFET's} - H03F 1/301: {in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence)} - H03F 3/193: with field-effect devices (H03F3/195 takes precedence) - H03F 2200/18: the bias of the gate of a FET being controlled by a control signal - H03F 2200/181: A coil being added in the gate circuit of a FET amplifier stage, e.g. for noise reducing purposes - H03F 2200/411: the output amplifying stage of an amplifier comprising two power stages - H03F 2200/447: the amplifier being protected to temperature influence - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/555: A voltage generating circuit being realised for biasing different circuit elements - H03F: AMPLIFIERS ## Abstract A multi-stage amplifier having a first amplifier stage comprising: a pair of transistors arranged in a cascade amplifier arrangement; and an isolation circuit; and a second amplifier stage coupled to an output of the first amplifier stage; and bias regulator having a reference transistor. The cascode amplifier stage includes a pair of transistors arranged in a cascode amplifier arrangement. The bias regulator produces a reference current through the reference transistor and DC bias voltages for the control electrodes of each of the pair of transistors in the cascode amplifier arrangement and for the second stage's transistor as a function of the reference current through the reference transistor. ## Claims ### Claim 1 An amplifier, comprising; a first amplifier stage comprising: a pair of transistors arranged in a cascode amplifier arrangement; and an isolation circuit; a second amplifier stage coupled to an output of the first amplifier stage; a voltage source coupled to the first amplifier stage and the second amplifier stage, the isolation circuit being coupled between the a pair of transistors arranged in a cascode amplifier arrangement, the voltage source producing a current serially through the isolation circuit and the pair of transistor in the cascode amplifier arrangement; a DC bias regulator comprising: a DC bias circuit for producing: a voltage related to a reference current produced by the DC bias circuit, such voltage being coupled to a control electrode of a first one of the pair of transistors; and a combiner having a pair of inputs coupled to: the voltage produced by the DC bias circuit and a voltage produced by the isolation circuit, respectively, to produce a DC bias voltage at a control electrode of a second one of the pair of transistors related to a combination of the voltage produced by the DC bias circuit and the voltage produced by the combiner. ### Claim 2 (depends on 1) The amplifier recited in claim 1 including a resistor connected between the pair of pair of transistor in the cascode amplifier arrangement. ### Claim 3 (depends on 1) The amplifier recited in claim 1 wherein the DC bias regulator, comprises: a reference transistor; wherein the DC bias regulator produce the reference current through the reference transistor; and wherein the DC bias regulator produces the DC bias voltages for each of the pair of transistors in the cascode amplifier arrangement as a function of the reference current produced through the reference transistor. ### Claim 4 (depends on 2) The amplifier recited in claim 2 including a resistor connected between the pair of transistors in the cascode amplifier arrangement. ### Claim 5 (depends on 1) The amplifier recited in claim 1 wherein the isolation circuit comprises a pair of serially connected resistors, the resistors being connected to a common junction, wherein the combiner includes a pair or resistors each one connected to a corresponding one of the pair of inputs of the combiner and to a combiner output, the combiner output being coupled to the control of the second one of the pair of transistors, one of the pair of inputs being connected to the junction. ### Claim 6 (depends on 5) The amplifier recited in claim 5 wherein the combiner circuit produces the DC bias voltage as a function of the sum of the output voltage produced by the reference voltage and the isolation circuit. ### Claim 7 (depends on 6) The amplifier recited in claim 6 wherein the combiner circuit produces the DC bias voltage as a function of the average of the output voltage produced by the reference voltage and the voltage produced by the isolation circuit. ### Claim 8 (depends on 7) The amplifier recited in claim 7 wherein the current through the reference transistor is a saturation current for the reference transistor and current from the voltage supply to the pair of transistors in the cascode amplifier arrangement is a saturation current for both the pair of transistors in the cascode amplifier arrangement. ### Claim 9 (depends on 7) The amplifier recited in claim 7 wherein the control electrode of a first one of the pair of transistors controls a flow of carriers between a first and second electrode of the first one of the pair of transistors in the cascode amplifier arrangement, and the control electrode of the second one of the pair of transistors in the cascode amplifier arrangement controls a flow of carriers between a first and second electrode of the second one of the pair of transistors in the cascode amplifier arrangement; and wherein the DC bias voltages produced at the control electrodes of the first one of the pair transistors in the cascode amplifier arrangement and the second one of the pair of transistor in the cascode amplifier arrangement produces a voltage across the first and second electrodes of the first one of the pair of transistors in the cascode amplifier arrangement equal to the voltage across the first and second electrodes of the second one of the pair of transistors in the cascode amplifier arrangement. ### Claim 10 (depends on 5) The amplifier recited in claim 5 wherein the resistances of the pair of resistors in the combiner are a function of the resistances of the pair of resistors in the isolation circuit and the resistance of the resistor between the pair of transistors in the cascode amplifier arrangement. ### Claim 11 (depends on 10) The amplifier recited in claim 10 wherein the combiner is a Millman passive combiner. ### Claim 12 (depends on 1) The amplifier recited in claim 1 wherein the a second amplifier stage includes a second stage transistor having a control electrode for controlling a flow of carriers between a first electrode and a second electrode and wherein the control electrode of the second stage transistor is coupled to the output of the first amplifier stage and wherein the first electrode of the second stage transistor is connected to the voltage source and the second electrode is connected to a reference potential. ### Claim 13 (depends on 12) The amplifier recited in claim 12 wherein: a first one of the electrodes of the second one of the transistors in the cascode amplifier arrangement is coupled to the voltage source through the isolation circuit; the second one of the electrodes of the second one of the pair of transistors is coupled to the second one of the electrodes of the first one of the pair of transistors in the cascode amplifier arrangement through a third resistor; and the second electrode of the first one of the pair of transistors in the pair of transistor in the cascode amplifier arrangement is coupled to the reference potential. ### Claim 14 (depends on 13) The amplifier recited in claim 13 wherein the first electrode of the second transistor is coupled to the control electrode of the second stage transistor. ### Claim 15 (depends on 14) The amplifier recited in claim 14 wherein the DC bias regulator, comprises: a reference transistor; wherein the DC bias regulator produce the reference current through the reference transistor; and wherein the DC bias regulator produces the DC bias voltages for each of the pair of transistors in the cascode amplifier arrangement as a function of the reference current produced through the reference transistor. ### Claim 16 (depends on 15) The amplifier recited in claim 15 wherein the isolation circuit comprises a pair of serially connected resistors, the resistors being connected to a common junction, wherein the combiner includes a pair or resistors each one connected to a corresponding one of the pair of inputs of the combiner and to a combiner output, the combiner output being coupled to the control of the second one of the pair of transistors, one of the pair of inmpiuts being connected to the junction. ### Claim 17 (depends on 16) The amplifier recited in claim 16 wherein the combiner circuit produces the DC bias voltage as a function of the sum of the output voltage produced by the reference voltage and the isolation circuit. ### Claim 18 (depends on 17) The amplifier recited in claim 17 wherein the combiner circuit produces the DC bias voltage as a function of the average of the output voltage produced by the reference voltage and the voltage produced by the isolation circuit. ### Claim 19 (depends on 16) The amplifier recited in claim 16 wherein the current through the reference transistor is a saturation current for the reference transistor and current from the voltage supply to the pair of transistors in the cascode amplifier arrangement is a saturation current for both the pair of transistors in the cascode amplifier arrangement. ### Claim 20 (depends on 12) The amplifier recited in claim 12 wherein the control electrode of a first one of the pair of transistors controls a flow of carriers between a first and second electrode of the first one of the pair of transistors in the cascode amplifier arrangement, and the control electrode of the second one of the pair of transistors in the cascode amplifier arrangement controls a flow of carriers between a first and second electrode of the second one of the pair of transistors in the cascode amplifier arrangement; and wherein the DC bias voltages produced at the control electrodes of the first one of the pair transistors in the cascode amplifier arrangement and the second one of the pair of transistor in the cascode amplifier arrangement produces a voltage across the first and second electrodes of the first one of the pair of transistors in the cascode amplifier arrangement equal to the voltage across the first and second electrodes of the second one of the pair of transistors in the cascode amplifier arrangement. ### Claim 21 (depends on 20) The amplifier recited in claim 20 wherein: a first one of the electrodes of the second one of the transistors in the cascode amplifier arrangement is coupled to the voltage source through the isolation circuit; the second one of the electrodes of the second one of the pair of transistors is coupled to the second one of the electrodes of the first one of the pair of transistors in the cascode amplifier arrangement through a third resistor; and the second electrode of the first one of the pair of transistors in the pair of transistor in the cascode amplifier arrangement is coupled to the reference potential. ### Claim 22 (depends on 21) The amplifier recited in claim 21 wherein the first electrode of the second transistor is coupled to the control electrode of the second stage transistor.