# US 9,520,776 B1 · Selective body bias for charge pump transfer switches > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,520,776 B1 - Document ID: US9520776B1 - Status: Granted - Kind: B1 - Application number: 14/989,666 - Filed: 2016-01-06 - Granted: 2016-12-13 - Earliest claimed: 2015-09-18 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies LLC - Inventors: Gooty Sukumar Reddy; Sridhar Yadala - Web page: https://patentgrep.com/patent/US9520776B1 ## CPC - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 16/30: Power supply circuits - H02M 3/073: {Charge pumps of the Schenkel-type} - H02M 3/075: {including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Techniques are presented for improving the efficiencies of multi-stage charge pumps by reducing the amount of voltage lost across the inter-stage transfer switches of the pump through use a selective body bias. The voltage level from both branches of one stage is each supplied though a corresponding diode to the bulk connection of the transfer switch after the subsequent stage in both branches. This arrangement results in each stage providing a largely uniform amount of gain, without the usual increase of voltage drop with increasing numbers of stages. ## Claims ### Claim 1 A charge pump, comprising: first and second branches connected in parallel between a supply node and an output node, wherein each of the branches includes a plurality of stages connected in series, the first of which is connected to the supply node though a respective initial switch, each stage having: a stage capacitor; a stage node connected to the corresponding stage capacitor; and a transfer switch, through which the corresponding stage node is connected to the stage node of the subsequent stage in the series, except for the final stage of the series, whose stage node is connected through the corresponding transfer switch to the output node, wherein, when the charge pump is enabled, even and odd stages in the series of the first branch are respectively connected to receive first and second clock non-overlapping clock signals and even and odd stages in the series of the second branch are respectively connected to receive the second and first clock signals; and first and second diodes through which the stage node of a first one of the stages in the series of both of the first and second branches are respectively connected to provide, for both of the first and second branches, a body bias of the transfer switches of the stage subsequent to the first one of the stages. ### Claim 2 (depends on 1) The charge pump of claim 1, wherein the transfer switches are transistor connected diodes having a gate connected to the corresponding stage node and the initial switches are diode connected transistors having a gate connected to the supply node. ### Claim 3 (depends on 1) The charge pump of claim 1, wherein for each of the stage capacitors, a first plate is connected to the corresponding stage node and a second plate is connected to receive the first clock signal for even stages of the first branch and odd stages of the second branch and to receive the second clock signal for odd stages of the first branch and even stages of the second branch. ### Claim 4 (depends on 1) The charge pump of claim 1, wherein the diodes are high threshold voltage devices. ### Claim 5 (depends on 1) The charge pump of claim 1, wherein the charge pump is formed on a non-volatile memory integrated circuit. ### Claim 6 (depends on 5) The charge pump of claim 5, wherein the charge pump generates programming voltages for use on the non-volatile memory integrated circuit. ### Claim 7 (depends on 5) The charge pump of claim 5, wherein the charge pump generates erase voltages for use on the non-volatile memory integrated circuit. ### Claim 8 (depends on 5) The charge pump of claim 5, wherein the charge pump generates sensing voltages for use on the non-volatile memory integrated circuit. ### Claim 9 (depends on 5) The charge pump of claim 5, wherein the non-volatile memory integrated circuit is a monolithic three-dimensional semiconductor memory device in which memory cells are arranged in multiple physical levels above a silicon substrate and word lines run in a horizontal direction relative to the substrate. ### Claim 10 (depends on 1) The charge pump of claim 1, wherein the first one of the stages in the series is the first stage of the series. ### Claim 11 (depends on 1) The charge pump of claim 1, wherein the first one of the stages in the series is the next to last stage in the series. ### Claim 12 An integrated circuit, comprising: an array of non-volatile memory cells; read, write, and erase circuitry connected to the array; and a charge pump, comprising: first and second branches connected in parallel between a supply node and an output node connectable to supply the read, write, and erase circuitry, wherein each of the branches includes a plurality of stages connected in series, the first of which is connected to the supply node though a respective initial switch, each stage having: a stage capacitor; a stage node connected to the corresponding stage capacitor; first and second diodes; and a transfer switch, through which the corresponding stage node is connected to the stage node of the subsequent stage in the series, except for the final stage of the series, whose stage node is connected through the corresponding transfer switch to the output node, wherein, when the charge pump is enabled, even and odd stages in the series of the first branch are respectively connected to receive first and second clock non-overlapping clock signals and even and odd stages in the series of the second branch are respectively connected to receive the second and first clock signals, and wherein the first and second diodes are connected through the stage node of a first one of the stages in the series of both of the first and second branches are respectively connected, for both of the first and second branches, to bias the body of the transfer switches of the stage subsequent to the first one of the stages. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein the transfer switches are transistor connected diodes having a gate connected to the corresponding stage node and the initial switches are diode connected transistors having a gate connected to the supply node. ### Claim 14 (depends on 12) The integrated circuit of claim 12, wherein for each of the stage capacitors, a first plate is connected to the corresponding stage node and a second plate is connected to receive the first clock signal for even stages of the first branch and odd stages of the second branch and to receive the second clock signal for odd stages of the first branch and even stages of the second branch. ### Claim 15 (depends on 12) The integrated circuit of claim 12, wherein the integrated circuit is a monolithic three-dimensional semiconductor memory device in which memory cells are arranged in multiple physical levels above a silicon substrate and word lines run in a horizontal direction relative to the substrate. ### Claim 16 (depends on 12) The integrated circuit of claim 12, wherein the first one of the stages in the series is the first stage of the series. ### Claim 17 (depends on 12) The integrated circuit of claim 12, wherein the first one of the stages in the series is the next to last stage in the series. ### Claim 18 (depends on 12) The integrated circuit of claim 12, wherein the charge pump generates programming voltages for the array. ### Claim 19 (depends on 12) The integrated circuit of claim 12, wherein the charge pump generates erase voltages for the array. ### Claim 20 (depends on 12) The integrated circuit of claim 12, wherein the charge pump generates sensing voltages for the array.